BS85B12-3 HOLTEK [Holtek Semiconductor Inc], BS85B12-3 Datasheet - Page 120

• Manufacturer Part Number: BS85B12-3
• Description: Touch Key Flash Type 8-Bit MCU with LCD/LED Driver
• Manufacturer: HOLTEK [Holtek Semiconductor Inc]

Rev. 1.00
Bit 7~6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
POR
R/W
Bit
SIMC2 Register
R/W
D7
Undefined bit
This bit can be read or written by user software program.
CKPOLB: Determines the base condition of the clock line
The CKPOLB bit determines the base condition of the clock line, if the bit is high, then the SCK
line will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK line will be
high when the clock is inactive.
CKEG: Determines SPI SCK active clock edge type
CKPOLB=0
CKPOLB=1
The CKEG and CKPOLB bits are used to setup the way that the clock signal outputs and
inputs data on the SPI bus. These two bits must be configured before data transfer is executed
otherwise an erroneous clock edge may be generated. The CKPOLB bit determines the base
condition of the clock line, if the bit is high, then the SCK line will be low when the clock is
inactive. When the CKPOLB bit is low, then the SCK line will be high when the clock is inactive.
The CKEG bit determines active clock edge type which depends upon the condition of CKPOLB
bit.
MLS: SPI Data shift order
This is the data shift select bit and is used to select how the data is transferred, either MSB or
LSB first. Setting the bit high will select MSB first and low for LSB first.
CSEN: SPI SCS pin Control
The CSEN bit is used as an enable/disable for the SCS pin. If this bit is low, then the SCS
pin will be disabled and as I/O function. If the bit is high the SCS pin will be enabled and used
as a select pin.
WCOL: SPI Write Collision flag
The WCOL flag is used to detect if a data collision has occurred. If this bit is high it means that
data has been attempted to be written to the SIMD register during a data transfer operation. This
writing operation will be ignored if data is being transferred. The bit can be cleared by the
application program.
TRF: SPI Transmit/Receive Complete flag
The TRF bit is the Transmit/Receive Complete flag and is set 1 automatically when an SPI
data transmission is completed, but must set to 0 by the application program. It can be used to
generate an interrupt.
7
0
0: the SCK line will be high when the clock is inactive
1: the SCK line will be low when the clock is inactive
0: SCK is high base level and data capture at SCK rising edge
1: SCK is high base level and data capture at SCK falling edge
0: SCK is low base level and data capture at SCK falling edge
1: SCK is low base level and data capture at SCK rising edge
0: LSB
1: MSB
0: Disable
1: Enable
0: No collision
1: Collision
0: Data is being transferred
1: SPI data transmission is completed
Touch Key Flash MCU with LCD/LED Driver
R/W
D6
6
0
CKPOLB
R/W
5
0
CKEG
R/W
114
4
0
MLS
R/W
3
0
BS85B12-3/BS85C20-3
CSEN
R/W
2
0
WCOL
R/W
1
0
February 1, 2011
TRF
R/W
0
0