PLL500-37 PhaseLink (PLL), PLL500-37 Datasheet - Page 3

• Manufacturer Part Number: PLL500-37
• Description: , Low Power CMOS Output Vcxo Family
• Manufacturer: PhaseLink (PLL)

2. AC Electrical Specifications
3. Voltage Control Crystal Oscillator
Note: Preliminary Specifications still to be characterized. Parameters denoted with an asterisk (*) represent nominal characterization data and are not
production tested to any specific limits.
4. Jitter and Phase Noise specification
Note: Preliminary Specifications still to be characterized.
47745 Fremont Blvd., Fremont, California 94538 TEL [phone] FAX [phone]
Input Crystal Frequency
Output Clock Rise/Fall Time
Output Clock Duty Cycle
Short Circuit Current
VCXO Stabilization Time *
VCXO Tuning Range
CLK output pullability
VCXO Tuning Characteristic
Pull range linearity
Power Supply Rejection
VIN pin input impedance
VIN modulation BW
RMS Period Jitter
(1 sigma – 1000 samples)
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
PARAMETERS
PARAMETERS
PARAMETERS
Low Power CMOS Output VCXO Family (27MHz to 200MHz)
SYMBOL
SYMBOL
T
PWSRR
VCXOSTB
with capacitive decoupling
between VDD and GND.
@100Hz offset
@1kHz offset
@10kHz offset
@100kHz offset
@1MHz offset
CONDITIONS
PLL500-27
PLL500-37
PLL500-47
0.8V ~ 2.0V with 10 pF load
0.3V ~ 3.0V with 15 pF load
Measured @ 1.4V
From power valid
XTAL C
0V
Frequency change with
Vdd varied +/- 10%
0V
VIN
VIN
CONDITIONS
CONDITIONS
0
/C
1
3.3V
3.3V, -3dB
< 250
Preliminary
MIN.
PLL500-27/-37/-47
MIN.
1000
300
45
MIN.
150
-1
TYP.
100
-110
-130
-138
-145
27
65
45
2.5
-80
TYP.
100
10
TYP.
MAX.
1.15
3.7
50
50
MAX.
UNITS
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
MAX.
Rev 10/20/03 Page 3
130
200
+1
65
55
5
ps
UNITS
UNITS
ppm/V
MHz
mA
ppm
ppm
ppm
kHz
ns
k
%
ms
%