PLL500-37 PhaseLink (PLL), PLL500-37 Datasheet - Page 2

• Manufacturer Part Number: PLL500-37
• Description: , Low Power CMOS Output Vcxo Family
• Manufacturer: PhaseLink (PLL)

PIN AND PAD DESCRIPTION
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
47745 Fremont Blvd., Fremont, California 94538 TEL [phone] FAX [phone]
Supply Voltage Range
Input Voltage Range
Output Voltage Range
Soldering Temperature
Storage Temperature
Ambient Operating Temperature
DRIVSEL
Name
XOUT
GND
VDD
CLK
XIN
VIN
OE
Pin#
1
2
3
4
5
2
7
8
Low Power CMOS Output VCXO Family (27MHz to 200MHz)
715.472
715.307
715.472
715.472
PARAMETERS
X ( m)
94.183
94.157
94.183
94.193
Die Pad Position
768.599
605.029
331.756
140.379
203.866
455.726
626.716
888.881
Y ( m)
Type
P
O
P
I
I
I
I
I
Crystal input pin.
Output drive select pin. High drive if set to ‘0’. Low drive if
set to ‘1’. Internal pull-up.
Frequency control voltage input pin.
Ground pin.
Output clock pin.
+3.3V VDD power supply pin. Only one VDD pin is necessary.
Output Enable input pin. Tri-states output if set to ‘0’.
Enables output if set to ‘1’. Internal pull-up.
Crystal output pin.
Preliminary
SYMBOL
V
V
T
V
CC
O
S
I
PLL500-27/-37/-47
Description
MIN.
-
-
-
-65
0.5
0.5
0.5
0
V
V
MAX.
CC
CC
260
150
70
7
+
+
0.5
0.5
Rev 10/20/03 Page 2
UNITS
V
V
V
C
C
C