PLL130-01 PhaseLink (PLL), PLL130-01 Datasheet - Page 2

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PLL130-01

Manufacturer Part Number
PLL130-01
Description
Output Level Converter Buffer , 750kHz - 700MHz In, 1 PaIR Outputs 1x, Pecl
Manufacturer
PhaseLink (PLL)
Datasheet
PIN DESCRIPTIONS
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other con-
ditions above the operational limits noted in this specification is not implied.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Supply Voltage Range
Input Voltage Range
Output Voltage Range
Soldering Temperature
Storage Temperature
Ambient Operating Temperature
OUT_SELECT
PECL_BAR
LVDS_BAR
GND_BUF
VDD_BUF
REF_IN
Name
LVDS
PECL
GND
VDD
N/C
N/C
OE
Number
PARAMETERS
9,15
1,2
6,7
10
11
12
13
14
16
3
4
5
8
Type
O
P
P
P
I
-
I
-
3.3V Power supply
Output selector. This pin has internal pull-up (defaults to 1 = LVDS).
Connect to GND (0) to select PECL outputs.
Not connected
Output Enable. This pin has internal pull-up (defaults to 1 = enabled).
Ground connector
Reference input signal. The frequency of this signal will be reproduced at
the output (after translation to LVDS or PECL level).
Ground connector for output buffer circuitry.
LVDS True output.
PECL True output.
3.3V Power supply for output buffer circuitry.
PECL Complementary output.
LVDS Complementary output.
Not connected
High Speed Buffer for LVDS and PECL
SYMBOL
Preliminary for proposal
V
V
T
V
CC
O
S
I
Description
MIN.
-
-
-
-65
0.5
0.5
0.5
0
PLL130-01
V
V
MAX.
CC
CC
260
150
70
7
+
+
0.5
0.5
Rev 07/13/01 Page 2
UNITS
V
V
V
C
C
C

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