UPD75238GJ NEC [NEC], UPD75238GJ Datasheet - Page 78

• Manufacturer Part Number: UPD75238GJ
• Description: 4 BIT SINGLE-CHIP MICROCOMPUTER
• Manufacturer: NEC [NEC]

78
(3) Event counter mode register
(4) Overflow flag (IRQT1)
(5) Event counter control register (GATEC)
The event counter mode register (TM1) is an 8-bit register that controls the event counter. Fig. 4-37 shows
the format of the register.
The TM1 is set with an 8-bit memory manipulation instruction. Bit 3 is an event counter start bit, and can
be set independently of the other bits. Bit 3 is automatically reset to 0 when the timer starts operation.
The overflow flag is set to 1 when the event counter (IRQT1) overflows. The flag is cleared to 0 by a count
operation start instruction.
This register specifies sampling by sampling clock (f
than two sampling clock cycles (8/f
Fig. 4-38 shows the format of the GATEC.
Address
FA8H
Address
FABH
7
0
Event count operation enable/disable bit
Event count start instruction bit
Count pulse edge specification
Fig. 4-38 Format of the Event Counter Control Register
Fig. 4-37 Format of the Event Counter Mode Register
TM12
TM13
TM14
6
0
3
0
When 1 is written, the counter and the IRQ1 flag are cleared.
IF TM12 is set to 1, count opertaion starts.
5
0
1
0
1
0
2
0
X
) as noise and accepts pulses wider than as interrupt signals.
TM14
Disables count operation (count value retained)
Enables count operation
TI0 input rising edge
TI0 input falling edge
4
1
0
TM13
GATEC0
3
0
X
/4). A noise eliminator eliminates pulses narrower
TM12
2
Symbol
GATEC
0
1
1
0
No sampling
Sampling at f
0
0
X
/4
Symbol
TM1
PD75238