UPD75238GJ NEC [NEC], UPD75238GJ Datasheet - Page 112

• Manufacturer Part Number: UPD75238GJ
• Description: 4 BIT SINGLE-CHIP MICROCOMPUTER
• Manufacturer: NEC [NEC]

112
(11) Serial interface (channel 1) operation
SCK1
SO1
EOT
SI1
(a) Operation halt mode
(b) Three-wire serial I/O mode operations
The operation halt mode is used when serial transfer is not performed. This mode reduces power
consumption.
Shift register 1 does not perform shift operation in this mode, so the shift register can be used as
a normal 8-bit register.
A RESET input sets the operation halt mode.
The P82/SO1 pin and P83/SI1 pin are fixed to function for input ports. The P81/SCK1 pin can be used
as an input port pin by setting serial operation mode register 1.
The three-wire serial I/O mode is compatible with other modes used in the 75X series and 78K series.
Communication is performed using three lines: Serial clock (SCK1), serial output (SO1), and serial
input (SI1).
The three-wire serial I/O mode transfers data with eight bits as one block. Data is transferred bit
by bit in phase with the serial clock.
Shift register 1 performs shift operation on the falling edge of the serial clock (SCK1). Send data
is latched on the SO1 latch, and is output on the SO1 pin.
Receive data applied to the SI1 pin is latched in the shift register 1 on the rising edge of SCK1.
When eight bits have been transferred, operation of shift register 1 automatically terminates setting
the serial transfer end flag (EOT).
Execution of instruction that writes data to SIO1 (Transfer operation start specification)
Fig. 4-61 Timing of the Three-Wire Serial I/O Mode
1
Transfer operation is started in phase with falling edge of SCK1.
DO7
DI7
2
DO6
DI6
3
DO5
DI5
4
DO4
DI4
5
DO3
DI3
6
DO2
DI2
7
DO1
DI1
Completion of transfer
8
DO0
DI0
PD75238