DS1822-PAR_07 DALLAS [Dallas Semiconductor], DS1822-PAR_07 Datasheet
DS1822-PAR_07
Related parts for DS1822-PAR_07
DS1822-PAR_07 Summary of contents
Page 1
... The DS1822-PAR digital thermometer provides 9- to 12-bit centigrade temperature measurements and has an alarm function with nonvolatile (NV) user-programmable upper and lower trigger points. The DS1822-PAR does not need an external power supply because it derives power directly from the data line (“parasite power”). The DS1822-PAR communicates over a 1-Wire bus, which by definition requires only one data line (and ground) for communication with a central microprocessor. It has an operating temperature range of -55° ...
Page 2
... The control line requires a weak pullup resistor since all devices are linked to the bus via a 3-state or open-drain port (the DQ pin in the case of the DS1822-PAR). In this bus system, the microprocessor (the master device) identifies and addresses devices on the bus using each device’s unique 64-bit code ...
Page 3
... Figure 1 shows the DS1822-PAR’s parasite-power control circuitry, which “steals” power from the 1-Wire bus via the DQ pin when the bus is high. The stolen charge powers the DS1822-PAR while the bus is high, and some of the charge is stored on the parasite power capacitor ( provide power when the bus is low ...
Page 4
... Only bits 11 through 4 of the temperature register are used in the T are 8-bit registers. If the measured temperature is lower than or equal alarm condition exists and an alarm flag is set inside the DS1822-PAR. This flag is updated after every temperature measurement; therefore, if the alarm condition goes away, the flag will be turned off after the next temperature conversion ...
Page 5
... Each DS1822-PAR contains a unique 64-bit code (see Figure 5) stored in ROM. The least significant eight bits of the ROM code contain the DS1822-PAR’s 1-Wire family code: 22h. The next 48 bits contain a unique serial number. The most significant eight bits contain a cyclic redundancy check (CRC) byte that is calculated from the first 56 bits of the ROM code ...
Page 6
... The CRCs provide the bus master with a method of data validation when data is read from the DS1822-PAR. To verify that data has been read correctly, the bus master must recalculate the CRC from the received data and then compare this value to either the ROM code CRC (for ROM reads the scratchpad CRC (for scratchpad reads) ...
Page 7
... If the bus is held low for more than 480μs, all components on the bus will be reset. In addition, to assure that the DS1822-PAR has sufficient supply current during temperature conversions necessary to provide a strong pullup (such as a MOSFET) on the 1-Wire bus whenever temperature conversions are taking place (as described in the PARASITE POWER section) ...
Page 8
... Step 2. ROM Command (followed by any required data exchange) Step 3. DS1822-PAR Function Command (followed by any required data exchange very important to follow this sequence every time the DS1822-PAR is accessed, as the DS1822-PAR will not respond if any steps in the sequence are missing or out of order. Exceptions to this rule are the Search ROM [F0h] and Alarm Search [ECh] commands ...
Page 9
... SIGNALING section for an explanation of alarm flag operation. DS1822-PAR FUNCTION COMMANDS After the bus master has used a ROM command to address the DS1822-PAR with which it wishes to communicate, the master can issue one of the DS1822-PAR function commands. These commands allow the master to write to and read from the DS1822-PAR’s scratchpad memory, initiate temperature conversions and determine the power supply mode ...
Page 10
... The master device can issue “read-time slots” (see the 1-WIRE BUS SYSTEM section) following the Recall E DS1822-PAR will indicate the status of the recall by transmitting 0 while the recall is in progress and 1 when the recall is done. The recall operation happens automatically at power-up, so valid data is available in the scratchpad as soon as power is applied to the device ...
Page 11
... MATCH DS1822-PAR T BIT 1 X MASTER T X DS1822-PAR T BIT 1 X BIT 1 MASTER T BIT BIT 1 BIT 1 MATCH? MATCH DS1822-PAR T BIT 63 X MASTER T DS1822-PAR T BIT BIT 63 MASTER T BIT BIT 63 BIT 63 MATCH? MATCH MASTER T X FUNCTION COMMAND ...
Page 12
... DS1822-PAR FUNCTION COMMANDS FLOW CHART Figure 10 MASTER T X FUNCTION COMMAND N B8h 2 RECALL MASTER BEGINS DATA 2 RECALL FROM E PROM DEVICE BUSY RECALLING DATA ? Y MASTER R “0s” X 44h N CONVERT TEMPERATURE ? Y MASTER ENABLES STRONG PULLUP ON DQ DS1822-PAR CONVERTS TEMPERATURE MASTER DISABLES STRONG PULLUP ...
Page 13
... There are two types of write-time slots: “Write 1” time slots and “Write 0” time slots. The bus master uses a Write 1 time slot to write a logic 1 to the DS1822-PAR and a Write 0 time slot to write a logic 0 to the DS1822-PAR. All write-time slots must be a minimum of 60μs in duration with a minimum of a 1μs recovery time between individual write slots ...
Page 14
... The DS1822-PAR samples the 1-Wire bus during a window that lasts from 15μs to 60μs after the master initiates the write-time slot. If the bus is high during the sampling window written to the DS1822- PAR. If the line is low written to the DS1822-PAR. READ/WRITE-TIME SLOT TIMING DIAGRAM Figure 12 ...
Page 15
... Output data from the DS1822-PAR is valid for 15μs after the falling edge that initiated the read- time slots. Therefore, the master must release the bus and then sample the bus state within 15μs from the start of the slot. Figure 13 illustrates that the sum of T Figure 14 shows that system timing margin is maximized by keeping T and by locating the master sample time during read-time slots towards the end of the 15μ ...
Page 16
... DS1822-PAR OPERATION EXAMPLE 2 In this example there is only one DS1822-PAR on the bus. The master writes to the T configuration registers in the DS1822-PAR scratchpad and then reads the scratchpad and recalculates the CRC to verify the data. The master then copies the scratchpad contents to EEPROM. ...
Page 17
... The Pullup Supply Voltage specification assumes that the pullup device (resistor or transistor) is ideal, and therefore the high level of the pullup is equal to V DS1822-PAR, the actual supply rail for the strong pullup transistor must include margin for the voltage drop across the transistor when it is turned on; thus ...
Page 18
... Start Convert T SPON Command Issued t SLOT t REC r LOW0 t LOW1 t RDV t RSTH t RSTL t PDHIGH t PDLOW IN/OUT DS1822-PAR Typical Performance Curve +3s Error Mean Error -3s Error Temperature (° 3.0V to 5.5V) PU MIN TYP MAX UNITS NOTES 93.75 ms 187.5 ms 375 ms 750 ms 10 µ ...
Page 19
... TIMING DIAGRAMS Figure DS1822-PAR ...