DS2722-F-03 MICRO-LINEAR [Micro Linear Corporation], DS2722-F-03 Datasheet - Page 23

• Manufacturer Part Number: DS2722-F-03
• Description: 900MHz Low-IF 1.5Mbps FSK Transceiver Final Datasheet
• Manufacturer: MICRO-LINEAR [Micro Linear Corporation]

REGISTER #0, PLL CONFIGURATION
PLL Charge Pump Polarity (QPP): DB0
This bit sets the charge pump polarity to sink or source current. For a majority of applications, this bit is cleared (QPP =
0). For applications where an external amplifier is in the loop filter, this bit is set to 1 to change the charge pump polarity
(see Table 7).
Reference Divide Bit Zero (RD0): DB1
This bit sets the reference division of the PLL to either 6 or 12 (see Table 8).
Receive Closed Loop Bit (RXCL): DB2
This bit is used in Receive mode to put the PLL into either open loop or closed loop (see Table 9).
PLL Frequency Shift Bit (LOL): DB3
LO shift for transmit and receive. For normal operations, it is recommended that LOL = 0 (see Table 10).
DS2722-F-05
QPP
0
1
RD0
0
1
LOL
Frequency signal < frequency reference. Charge pump sources current.
0
1
Frequency signal < frequency reference. Charge pump sinks current.
REFERENCE DIVISION
Table 9. PLL Mode in Normal Receive Operation
LO SHIFT FOR TRANSMIT
FINAL DATASHEET
Table 8. Reference Frequency Select
12
Table 7. PLL Charge Pump Polarity
6
+1.024 MHz
RXCL
Table 10. PLL Frequency Shift
0
1
PLL CHARGE PUMP POLARITY
0
RECEIVE PLL MODE
PLL closed loop
PLL open loop
NOMINAL REFERENCE FREQUENCY
LO SHIFT FOR RECEIVE
12.288 MHz
6.144 MHz
+1.024 MHz
DECEMBER 2003
0
ML2722
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