pe-68531g Pulse Specialty Components, pe-68531g Datasheet - Page 3

• Manufacturer Part Number: pe-68531g
• Description: Pe-6853xg Fastpulse High Speed Transceivers
• Manufacturer: Pulse Specialty Components

The transceiver provides all Physical Media Dependent (PMD)
functions required to allow digital Physical layer controller to
send/receive data integrally over the twisted pair media.
The TP-FDDI/100Base-TX PHY chip set will perform clock
recovery/generation, scrambling, 4B/5B codec, serial-parallel
conversion, etc. These functions are available from several
vendors in different chip set partitioning. Please refer to vendor list
in appendix for more information. The PECL interface is a stan-
dard interface used by fiber optic transceivers in FDDI and
100Base-FX applications. Since 100Base-TX employs the basic
TP-FDDI PMD scheme, the PE-68531G and PE-68537G are
electrically identical with different RJ-45 pinouts as per the
standards (refer to pinout specification). The PE-68537G fits the
FASTPULSE HIGH SPEED
LAN TRANSCEIVERS
System Application
ATM155/100Base-TX
Note: Two Mechanical Stake Posts are connected to RJ-45
Signal Pin #
GND
GND
U.S.A: TEL [phone]
RD+
SD+
TD+
RD-
Vcc
Vcc
TD-
Notes:
ATM Controllers: Texas Instruments, PMC, Fujitsu, AMCC . . .
100BTX/FDDI Controllers: National Semiconductor, AMD, Motorola . . .
Shield and Body Shield.
1
2
3
4
5
6
7
8
9
DECODER
ENCODER
Description
Analog Ground
Differential Receive Data +
Differential Receive Data -
Signal Detect Output
Power Supply Voltage
Power Supply Voltage
Differential Transmit Data -
Differential Transmit Data +
Analog Ground
Pin Descriptions
PHYSICAL CONTROLLER
FRAMING
FRAMING
EUROPE: TEL [phone]
SYNC.
GENERATION
SERIAL TO
PARALLEL
PARALLEL
TO SERIAL
RECOVERY
I/O
—
—
—
—
O
O
O
CLOCK
CLOCK
I
I
Supply
Supply
Supply
Supply
Type
PECL
PECL
PECL
PECL
PECL
3
following Fast Ethernet product architectures: 100Base-TX only
with adapter and repeater, 10/100 adapter with separate 10/100
RJ-45 connectors.
The ATM PHY chip set will perform clock recovery/generation,
serial-parallel conversion, framing, scrambling, cell extraction/
insertion, etc. These functions are available from several vendors
in different chip set partitioning. The PECL interface is a standard
interface used by fiber optic transceivers in ATM applications.
The PE-68532G and the PE-68538G are electronically identical
but have “mirror” RJ-45 pinouts as required by standard for
adapter (user) node and switch (hub) node of network
respectively (refer to pinout specification).
Note: Unused pairs (P1, P2) are terminated onboard
ASIA: TEL [phone]
Pin # PE-68531/32G
NRZ DATA
(PECL)
RD±
TD±
1
2
3
4
5
6
7
8
Transmit (TX+)
Receive (RX+)
Transmit (TX-)
Receive (RX-)
Unused P1
Unused P2
Unused P2
Unused P1
PMD TRANSCEIVER
FASTPULSE
RJ-45 Connector Pinout
WEB: http://www.pulseeng.com
PE-68537G
Transmit (TX+)
Receive (RX+)
Transmit (TX-)
Receive (RX-)
Unused P1
Unused P1
Unused P2
Unused P2
H309.A (7/96)
PE-68538G
Receive (RX+)
Transmit (TX+)
Transmit (TX-)
Receive (RX-)
Unused P1
Unused P2
Unused P2
Unused P1
TWISTED
MEDIA
PAIR