em6521 EM Microelectronic, em6521 Datasheet - Page 44

• Manufacturer Part Number: em6521
• Description: Mfp Version Of Em6621 Ultra Low Power Microcontroller With 4x20 Lcd Driver
• Manufacturer: EM Microelectronic

11 Supply Voltage Level Detector
The EM6521 has a built-in Supply Voltage Level Detector (SVLD) circuitry, such that the CPU can compare the
supply voltage against a pre-selected value. During sleep mode this function is inhibited.
The CPU activates the supply voltage level
detector by writing VldStart = 1 in the register
RegVldCntl . The actual measurement starts on
the next Ck[9] rising edge and lasts during the
Ck[9] high period (2 ms at 32 KHz). The busy
flag VldBusy stays high from VldStart set until
the measurement is finished. The worst case
time until the result is available is 1.5 Ck[9]
prescaler clock periods (32 KHz -> 6 ms). The
detection level must be defined in register
RegVldLevel before the VldStart bit is set.
During the actual measurement (2 ms) the
device will draw an additional 5 µA of IV
current. After the end of the measure the result
is available by inspection of the bit VldResult .
If the result is read 0, then the power supply
voltage was greater than the detection level
value. If read 1, the power supply voltage was lower than the detection level value. During each read while
Busy=1 the VldResult is not guaranteed. For compatibility reasons the SVLD levels available on the EM6521
are kept the same as the levels used on the EM6621. This means that all levels which may be lower2.0V could
not be reached anymore because they are below V
11.1 SVLD Register
Table 11.1.1 Register RegVldCntl
Table 11.1.2 Register RegVldLevel (Detection Level Value)
Table 11.1.3 Voltage Level Detector Value Selecting
*1
**2 levels which are too far below V
Copyright © 2005, EM Microelectronic-Marin SA
Level1
Level2
Level3
Level4
Level5
Level6
Level7
Level8
level which may not be reached anymore because it can be lower than V
Bit
Bit
3
2
2
1
0
3
2
1
0
R*; Read value while VLDBusy=1 is not guaranteed.
R
VldLevel2
NoLogicWD
NoOscWD
VldLevel2
VldLevel1
VldLevel0
VldResult
VldBusy
VldStart
Name
Name
0
0
0
0
1
1
1
1
--
DD
VldLevel1
Reset
Reset
min to be reached. (Are here for software compatibility with EM6621).
0
0
0
0
0
x
0
0
0
0
0
1
1
0
0
1
1
DD
Figure 32. SVLD Timing Diagram
Compare Level
DD
Ck[9] (256 Hz)
VBAT =V
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read Result
R*
min.
W
R
--
Busy Flag
Measure
Result
VldLevel0
DD
44
0
1
0
1
0
1
0
1
CPU starts
measure
SVLD < VBAT
No Oscillator watchdog
No logic watchdog
Vld level selection
Vld level selection
Vld level selection
DD
0
Vld result flag
Vld busy flag
min.
Description
Description
not active
Vld start
Typical voltage level
CPU starts
measure
SVLD > VBAT
1.70**2
1.45**2
1.30**2
1,20**2
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1.95*1
4.00
2.95
2.35
EM6521
1