pl-3507d-lf Prolific Technology Inc., pl-3507d-lf Datasheet - Page 11

• Manufacturer Part Number: pl-3507d-lf
• Description: Pl-3507 For Chip Rev D Hi-speed Usb & Ieee 1394 Combo To Ide Bridge Controller
• Manufacturer: Prolific Technology Inc.

6.0 Pin Assignment & Description
6.1 GPIO (ATA / ATAPI Interface)
GP1[0] : IDERSTJ
GP1[1] : DIOWJ
GP1[2] : DIORJ
GP1[3] : DMACKJ
GP1[4] : IORDY
GP1[5] : INTRQ
GP1[6] : DMARQ
GP1[7] : PROM_ADDR[15]
GP0[0] : DA0
GP0[1] : DA1
GP0[2] : DA2
GP0[3] : CSJ0
GP0[4] : CSJ1
GP0[5] : PROM_WR
GP0[6] : PROM_CE
GP0[7] : USBVCC
DMA_DIO[0:7]
DMA_DIO[8:15]
PL-3507D Product Datasheet
: STOP
: HDMARDYN
: HSSTROBE
: DDMADRDYN
: DSTROBE
Name
Table 6-1 Pin Assignment & Description [GPIO (ATA/ATAPI Interface)]
107~114
116~123
Pin No.
124
125
126
10
12
13
14
11
2
3
4
6
7
8
9
5
I/O (O) Reset signal of ATA/ATAPI devices
I/O (O)
I/O (O)
I/O (O) DMA acknowledge to ATA/ATAPI devices
I/O (O)
I/O (O)
I/O (O)
I/O (O)
I/O (O)
I/O (I)
I/O (I)
I/O (I)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
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(DIOWJ): For modes other than ultra DMA burst
in/out, this is a write strobe signal.
(STOP): For ultra DMA burst in/out, host can use
this signal to stop ultra DMA burst transfer.
(DIORJ): For modes other than ultra DMA burst
in/out, this is a read strobe signal.
(HDMARDYN): For ultra DMA data in burst, it is
asserted by host to indicate to the device that the
host is ready to accept ultra DMA burst in data.
(HSSTROBE): For ultra DMA data out burst, this
signal is a data strobe signal from host.
(IORDY): For PIO mode 3 and above, this signal is
negated to extend the transfer cycle of any host
ATA register access.
(DDMADRDYN): For ultra DMA data out burst, it is
asserted by ATA device to indicate to the host that
the device is ready to accept ultra DMA burst out
data.
(DSTROBE): For ultra DMA data in burst, this
signal is a data strobe signal from device.
ATA/ATAPI interrupt request
DMA request from ATA/ATAPI devices
External ROM/Flash address bit [15]
Device address bus, used by host to access a
register or data port in the storage device.
Device address bus, used by host to access a
register or data port in the storage device.
Device address bus, used by host to access a
register or data port in the storage device.
Chip select signal from host, used to select the
command block registers.
Chip select signal from host, used to select the
control block registers.
External flash write signal
External flash chip enable signal
USBVCC input through a 10k resistor
Bidirectional data bus between the host and
storage device.
Bidirectional data bus between the host and
storage device.
Description
ds_pl3507D_v1.1.doc
Document Version 1.1
August 28, 2007
Revised Date: