pl-3507d-lf Prolific Technology Inc., pl-3507d-lf Datasheet
pl-3507d-lf
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pl-3507d-lf Summary of contents
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... PL-3507 (For Chip Rev D) Hi-Speed USB & IEEE 1394 Combo to IDE Bridge Controller Product Datasheet Document Revision: 1.1 Document Release: August 28, 2007 Prolific Technology Inc. 7F, No. 48, Sec. 3, Nan Kang Rd. Nan Kang, Taipei 115, Taiwan, R.O.C. Telephone: +886-2-2654-6363 Fax: +886-2-2654-6161 E-mail: sales@prolific.com.tw Website: http://www ...
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... All the information in this document is subject to change without prior notice. Prolific Technology Inc. does not make any representations or any warranties (implied or otherwise) regarding the accuracy and completeness of this document and shall in no event be liable for any loss of profit or any other commercial damage, including but not limited to special, incidental, consequential, or other damages. ...
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... Update datasheet to add Chip Rev 2D information 1.0C Section 3: Modify Functional Block Diagram 1.0B Note: Chip Rev 1D does not support internal ROM code and requires external Flash to load firmware. 1.0A PL-3507 (Chip Rev D) Datasheet – Formal Release 0.9A PL-3507 (Chip Rev D) Datasheet – Preliminary Release PL-3507D Product Datasheet Description - 3 - Revised Date: August 28, 2007 ds_pl3507D_v1 ...
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... Program and External Data Memory ................................................................... 15 7.4 External Flash Memory Programming Control..................................................... 16 8.0 DC CHARACTERISTICS ................................................................................17 8.1 Absolute Maximum Ratings ................................................................................. 17 8.2 Recommended Operating Conditions.................................................................. 17 8.3 Leakage Current and Capacitance ...................................................................... 17 8.4 Recommended Supply Voltage & Operating Junction Temperature Ranges ...... 18 9.0 ORDERING INFORMATION ...........................................................................18 10.0 OUTLINE DIAGRAM.......................................................................................19 PL-3507D Product Datasheet Table of Contents - 4 - Revised Date: August 28, 2007 ds_pl3507D_v1 ...
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... Figure 3-1 Block Diagram of PL-3507D (Chip Rev D) .............................................................. 8 Figure 4-1 System Application Diagram of PL-3507D (Chip Rev D)......................................... 9 Figure 5-1 Pin Assignment Outline of PL-3507 (Chip Rev D) ................................................. 10 Figure 10-1 Outline Diagram of PL-3507 LQFP128................................................................ 19 Table 6-1 Pin Assignment & Description [GPIO (ATA/ATAPI Interface)] ................................. 11 Table 6-2 Pin Assignment & Description [1394 PHY-Link Interface] ....................................... 12 Table 6-3 Pin Assignment & ...
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... Provides auto-detect function to select active device between USB and 1394 IEEE 1394-1995 and IEEE P1394a Compliant Universal Serial Bus Specification 1.1 and 2.0 Compliant USB Mass Storage Class Bulk-Only Transport Specification Compliant. No driver installation needed in Windows ME or above, Mac OS 9.x or above, and Linux (kernel 2.4.18 or above). Windows 98 requires additional driver installation provided by Prolific. ...
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... Product Overview The PL-3507 is a high performance combo bridge solution for connecting USB 2.0 and 1394 to ATA or ATAPI data storage devices, e.g. hard disk drives, CD-ROM, CD-R, CD-RW and DVD. The USB interface of PL-3507 supports USB 1.1 or USB 2.0 specifications to allow connections to host computer via USB port at maximum data transfer rate 480 Mbps. ...
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... DIO[7:0] LREQ 1394 SBP2 LPS Link Layer LINKON SCLK DP USB UTMI & DN USB Link Layer Program SRAM Figure 3-1 Block Diagram of PL-3507D (Chip Rev D) PL-3507D Product Datasheet FIFO ATA/ATAPI Interface MMU Program 8032 ROM - 8 - Revised Date: August 28, 2007 ds_pl3507D_v1.1.doc DMA_DIO[15:0] GP0[7:0] GP1[7:0] Document Version 1 ...
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... System Application Diagram ATA/ATAPI signals ADDR[14:0] ROM/ FLASH DATA[7:0] Figure 4-1 System Application Diagram of PL-3507D (Chip Rev D) PL-3507D Product Datasheet IDE SLOT Regulator P2[6:0],P0[7:0] PL3507 P1[7:0] 1394 PHY-LINK interface signals 1394 PHY - 9 - Revised Date: August 28, 2007 ds_pl3507D_v1.1.doc 3.3V USB_DP USB_DM TPA0 TPB0 TPA1 TPB1 ...
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... Pin Assignment Outline Figure 5-1 Pin Assignment Outline of PL-3507 (Chip Rev D) PL-3507D Product Datasheet - 10 - Revised Date: August 28, 2007 ds_pl3507D_v1.1.doc Document Version 1.1 ...
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... GP0[4] : CSJ1 GP0[5] : PROM_WR GP0[6] : PROM_CE GP0[7] : USBVCC DMA_DIO[0:7] 107~114 DMA_DIO[8:15] 116~123 PL-3507D Product Datasheet I/O 124 I/O (O) Reset signal of ATA/ATAPI devices (DIOWJ): For modes other than ultra DMA burst in/out, this is a write strobe signal. 125 I/O (O) (STOP): For ultra DMA burst in/out, host can use this signal to stop ultra DMA burst transfer ...
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... PL-3507D Product Datasheet I/O I/O 1394 PHY-LINK control bus I/O 1394 PHY-LINK data bus 53 O 1394 Link layer request indicator 44 I 1394 System clock supplied by PHY. 49.152MHz 57 O 1394 Link power status 58 I 1394 Link power on request signal from PHY 59 O Power down 1394 PHY 60 I Cable power status input from 1394 PHY ...
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... GND 30, 31, 63, 89, 127, 128 AGND 93, 97, 102 6.8 Extra GPIO Pins Table 6-8 Pin Assignment & Description [Extra GPIO Pins] Name Pin No. EGPIO[0:5] 81~86 PL-3507D Product Datasheet I Reset signal, active low 87 I Program memory test mode I 00: Normal operation mode 74 I ...
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... Mbytes/sec. When connecting to host computers through USB cable, host computer will get device descriptor from the PL-3507 in order to be recognized as a mass storage class device, and then the host can start to transfer data to/from ATA/ATAPI devices through the PL-3507. PL-3507D Product Datasheet ...
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... EGPIO[5] is connected to internal USB remote wake-up port that can wake-up the PL-3507 from sleep mode. All the sources of interrupt 1 can wake-up the PL-3507 from sleep mode no matter how PL-3507 went to sleep either from USB or 1394. ...
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... FT8032 for intended data and flash control register for read/write control. The starting address of USB firmware code should be located at “0000h” in the external flash, and 1394 firmware code should be at “8000h”. PL-3507D Product Datasheet - 16 - Revised Date: August 28, 2007 ds_pl3507D_v1 ...
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... Input Voltage of 3.3V I/O with 5V Tolerance Storage Temperature T STG 8.2 Recommended Operating Conditions Table 8-2 Recommended Operating Conditions SYMBOL PARAMETER Core Power Supply V , DD25 USB_V DD25 Power Supply of 3.3V I/O V CC33 Power Supply of USB PHY USB_V CC33 Power Supply of Regulator REG_V CC Power Supply of Regulator REG_25V OUT Input Voltage of 3.3V I/O VIN 3 Input Voltage of 3 ...
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... PU/ PD resistance 9.0 Ordering Information Part Number PL-3507D PL-3507D-LF Note: The chip version can be found on the chip-marking showing: “YYWW2D” (datecode + chip version). Where: YY – last two digits of the year WW – week of the year 2D – chip version Example: “06102D” – means year 2006 + week no chip version. ...
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... Outline Diagram Figure 10-1 Outline Diagram of PL-3507 LQFP128 PL-3507D Product Datasheet - 19 - Revised Date: August 28, 2007 ds_pl3507D_v1.1.doc Document Version 1.1 ...