ch7011a Chrontel, ch7011a Datasheet - Page 42

• Manufacturer Part Number: ch7011a
• Description: Ch7011 Tv Output Device
• Manufacturer: Chrontel

CHRONTEL
8.3 Clock - Master, Sync - Master Mode
42
Table 29. Timing for Clock - Master, Sync - Slave Mode
P-OUT
H
V
XCLK
XCLK*
D[11:0]
Symbol
t1
t2
t3
t4
t5
t6
t7
DE
Parameter
P-OUT rise/fall time w/15pF load, VREF = 1.65 V
XCLK & XCLK* rise/fall time w/15pF load
Setup time:
Differential Clock: (XCLK = XCLK*) to (D[11:0], H, V & DE = VREF)
Single-ended Clock: (XCLK =VREF) to (D[11:0], H, V & DE = VREF)
Hold time
Differential Clock: (XCLK = XCLK*) to (D[11:0], H, V & DE = VREF)
Single-ended Clock: (XCLK =VREF) to (D[11:0], H, V & DE = VREF)
D[11:0], H, V & DE rise/fall time w/15pF load
Hold time:
P-OUT to HSYNC, VSYNC delay
(P-OUT=VREF) to (XCLK =XCLK*) delay
V
V
V
V
V
V
V
V
V
V
V
V
V
V
OH
OL
OH
OL
OH
OL
IH
IL
IH
IL
IH
IL
IH
IL
Figure 19: Clock - Master, Sync - Master Mode
t6
t5
64 PIXELS
1 VGA
Line
t5
t2
t7
Min
t1
0.5
0.5
201-0000-037 Rev 2.1, 10/20/2004
P0a
t3
Typ
P0b
1.5
3
3
3
t3
t1
P1a
P1b
Max
CH7011A
t4
P2a
P2b
t5
Unit
ns
ns
ns
ns
ns
ns
ns