ch7008a Chrontel, ch7008a Datasheet - Page 32

• Manufacturer Part Number: ch7008a
• Description: Digital Pc To Tv Encoder
• Manufacturer: Chrontel

CHRONTEL
Register Descriptions (continued)
PLL Overflow Register
The PLL Overflow Register contains the MSB bits for the’M’ and ’N’ values, which will be described in the PLL-M
and PLL-N registers, respectively. The reserved bits should not be written to.
PLL M Value Register
The PLL M value register determines the division factor applied to the frequency reference clock before it is input to
the PLL phase detector when the CH7008 is operating in master mode. In slave mode, an external pixel clock is
used instead of the frequency reference, and the division factor is determined by the XCM[3:0] value. This register
contains the lower 8 bits of the complete 9-bit M value.
32
Bit:
Symbol:
Type:
Default:
Bit:
Symbol:
Type:
Default:
Figure 17: Luma Transfer Function at different contrast enhancement settings.
7
7
M7
R/W
0
6
6
M6
R/W
1
256
224
192
160
128
96
64
32
0
0
5
5
M5
R/W
0
32
64
96
4
Reserved
R/W
0
4
M4
R/W
0
128
160
3
Reserved
R/W
0
3
M3
R/W
0
192
224 256
2
N9
0
2
M2
0
201-0000-027 Rev 2.8, 6/24/2004
R/W
R/W
Address: 13H
Bits: 5
Symbol: PLLM
Address: 14H
Bits: 8
Symbol: MNE
1
N8
R/W
0
1
M1
R/W
0
CH7008A
0
M8
R/W
0
0
M0
R/W
1