sii1161 Silicon image, sii1161 Datasheet - Page 6

• Manufacturer Part Number: sii1161
• Description: Panellink Receiver
• Manufacturer: Silicon image

Functional Description
The SiI 1161 is a DVI 1.0 compliant PanelLink receiver in a compact package. It provides 24 or 48 bits for data
output, and allows for panel support up to UXGA. Figure 1 shows the functional blocks of the chip.
The PanelLink TMDS core accepts as inputs the three TMDS differential data lines and the differential clock. The
core senses the signals on the link and properly decodes them providing accurate pixel data. The core outputs
the necessary sync signals (HSYNC, VSYNC), clock (ODCK), and a DE signal that goes high when the active
region of the video is present.
The SCDT signal is output when there is active video on the DVI link and the PLL in the TMDS has locked on to
the video. SCDT can be used to trigger external circuitry, indicating that an active video signal is present or used
to place the device in power down when no signal is present (by tying it to PDO#). The EXT_RES component is
used for impedance matching.
SiI-DS-0096-D
STAG_OUT#
HS_DJTR
EXT_RES
OCK_INV
RXC+
PDO#
RX2+
RX1+
RX0+
PIXS
RX2-
RX1-
RX0-
RXC-
SDA
SCL
ST
Control Registers
Equalization
Termination
VCR
VCR
VCR
VCR
-----------
Control
and
Figure 1. Functional Block Diagram
Data Recovery
Data Recovery
Data Recovery
CH2
CH1
CH0
PLL
SYNC2
SYNC1
SYNC0
2
Channel
SYNC
Decoder
Interface
Panel
Logic
SiI 1161 PanelLink Receiver
QO[23:0]
QE[23:0]
CTL[3:1]
HSYNC
VSYNC
ODCK
SCDT
DE
Data Sheet