mu9c8338a Music Semiconductors, Inc., mu9c8338a Datasheet - Page 23

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mu9c8338a

Manufacturer Part Number
mu9c8338a
Description
Mu9c8338a 10/100mb Ethernet Filter Interface
Manufacturer
Music Semiconductors, Inc.
Datasheet
Capacitance
TIMING DIAGRAMS
Host Processor
Table 33: Host Processor Interface Timing Data
Rev. 0a
No.
Symbol
10
11
12
13
C OUT
1
2
3
4
5
6
7
8
9
C IN
C I0
/WRITE (read)
/PCS (/PCSS)
tPRHPRL
D[15:0](read)
tCHPRH
PROC_RDY
Symbol
tPLPRL
tPHDZ
tWVPL
tPLWX
tCHDV
tDVPH
tPHDX
tPLDX
tPHPL
tAVPL
tPLAX
Parameter
Input Capacitance
Output Capacitance
Bi-directional Capacitance
SYSCLK
A[7:0]
Parameter (ns)
/PCS (/PCSS) LOW to D(15:0) enable
/PCS (/PCSS) HIGH to D(15:0) disable
/WRITE setup to /PCS (/PCSS)
/WRITE hold from /PCS (/PCSS)
SYSCLK HIGH to D(15:0) (read)
D(15:0) setup to /PCS (/PCSS) HIGH (write)
D(15:0) hold from /PCS (/PCSS) HIGH (write)
PROC_RDY delay from SYSCLK HIGH
A(7:0) setup to /PCS (/PCSS) LOW
A(7:0) hold from /PCS (/PCSS) LOW
/PCS (/PCSS) HIGH time
/PCS (/PCSS) to PROC_RDY LOW
PROC_RDY HIGH time
Figure 7: Host Processor Interface - Read Sequence
t3
t9
t12
t4
t10
t1
23
t5
t8
t13
Typ
10
6
9
2*SYSCLK+8
1*SYSCLK
t2
Min
10
3
3
5
3
5
3
Units
pF
pF
pF
t11
Notes
f = 1 MHz, V IN = 0 V
f = 1 MHz, V OUT = 0 V
f = 1 MHz, V I0 = 0 V
SYSCLK+5
SYSCLK+5
Max
10
10
Notes

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