mu9c4320l-90tdi Music Semiconductors, Inc., mu9c4320l-90tdi Datasheet
mu9c4320l-90tdi
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mu9c4320l-90tdi Summary of contents
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... MU9C4320L ATMCAM MU9C4320L ATMCAM MU9C4320L ATMCAM MU9C4320L ATMCAM APPLICATION BENEFITS • High performance VPI/VCI translation for ATM switches and routers OC-48 • Fully deterministic translation, independent from the size of the list and the length of VPI/VCI • Pipelined architecture for increased throughput • ...
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... MU9C4320L ATMCAM GENERAL DESCRIPTION The MU9C4320L ATMCAM Content Addressable Memory (CAM) with a 32-bit wide data interface. The device is designed for use in ATM switches and routers to provide very high throughput VPI/VCI translation through lookup tables held in external RAM. VPI/VCI fields from the ATM cell header are compared against a list of current connections stored in the CAM array ...
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... The ATMCAM supports simple daisy chained vertical cascading that serves to prioritize multiple devices and provides system-level match and full indication. If the slight timing overhead associated with the daisy chain is unacceptable in the fastest systems, the ATMCAM is designed to facilitate external prioritization across multiple devices. 3 MU9C4320L ATMCAM ...
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... MU9C4320L ATMCAM PIN DESCRIPTIONS Note: Signal names that start with a slash (“/”) are active LOW. All signals are 3.3V CMOS level. Never leave inputs floating. The CAM architecture draws large currents during compare operations, mandating the use of good layout and bypassing techniques. Refer to the Electrical Characteristics section for more information. DQ31– ...
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... HIGH, the /MF output will only go LOW if there is a match during a Comparison cycle; when the /MI input is LOW, the /MF output will go LOW. The /MF output from one device is connected to the /MI input of the next lower-priority device. The /MI pin of the highest-priority device must be tied HIGH. 5 MU9C4320L ATMCAM ...
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... MU9C4320L ATMCAM /FF (Full Flag, Output) The /FF output indicates when all the memory locations have their Validity bits set valid (LOW). When there is at least one location with its Validity bit set HIGH, the /FF output will be HIGH; when all locations have their Validity bits set LOW, and the /FI input is LOW, the /FF output will be LOW ...
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... The ATMCAM supports VP Table lookup in parallel with VPI/VCI comparison in the CAM array. This option is selected through the Configuration register. When active, Comparand Register bits CR31–20 are used to address the Table simultaneously with the Compare cycle. 7 MU9C4320L ATMCAM Only the ...
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... MU9C4320L ATMCAM The results of the Compare cycle have higher priority than the VP Table lookup, and take precedence over it. In the absence of a match in the CAM, the single bit accessed in the VP Table is used to indicate whether there was a VP Table match. Results of the Comparison cycle and VP Table lookup are indicated through the /MV and /MF outputs ...
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... VP Table bits can be read, set, and reset. The table is accessed during a Compare cycle. The single bit that is accessed in the VP Table by the address formed from Comparison data bits 31–20 is used to indicate whether there Table match at that address. The 9 MU9C4320L ATMCAM ...
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... MU9C4320L ATMCAM individual bits in the VP Table are set and reset through control states. A LOW value in the VP Table indicates a match, while a HIGH value indicates a mismatch. The results of comparison in the CAM array have a higher priority than the VP Table result. In other words, if there is a match in the CAM array, the VP Table result is ignored, and the match is flagged by /MV and /MF going LOW ...
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... A Read cycle with /AV HIGH accesses the Status register. Rev. 3 MU9C4320L ATMCAM Active Address Interface PA3–0:AA11–0 The Active Address interface PA3–0:AA11–0 carries the currently active address. The address source depends on the most recent control state that caused it to change ...
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... MU9C4320L ATMCAM PA3–0:AA11–0 After a Write at Next Free Address Cycle After a Write at Next Free Address cycle the PA3–0:AA11–0 lines carry the address that was written to during that cycle. Only the device in which the write occurred enables its PA3–0:AA11–0 lines. All other devices keep their PA3– ...
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... Match address, Memory Access address, VP Table address, or Reset state. Bits SR19–16 hold the Page address, PA3–0, for the device. Bits SR11–0 hold the Active address, AA11–0. All other bits are reserved and are set LOW. See Table 4 on page 26. 13 MU9C4320L ATMCAM ...
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... MU9C4320L ATMCAM Next Free Address Register The 32-bit Next Free Address register holds the highest-priority address that has its Validity bit set empty (LOW). System-level prioritization ensures that only the device with the highest-priority empty address in a vertically cascaded system will respond to a Read Next Free Address Register Control state. Bits NF19– ...
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... The ATMCAM architecture supports external prioritization for cases where the daisy chain overhead proves unacceptable. Figure 4 shows a system in which a number of ATMCAMs are vertically cascaded. in high impedance. Figure 4: Vertically Cascading ATMCAMs 15 MU9C4320L ATMCAM '1' '0' +3.3V /MI /FI /MV ATMCAM (Highest Priority) /MF ...
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... MU9C4320L ATMCAM FULL Cascading The Full flag is set LOW in a particular ATMCAM if the /FI line is LOW, and that device is full. During a Write cycle, the Full flag will not change until /E goes HIGH during that cycle. When the /FI line is HIGH, one or more locations are free in the higher-priority devices; therefore, when the /FI line is HIGH, whether or not that particular device is full, its /FF output will remain HIGH ...
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... The sequence continues until all Page Address values have been written. The RST FF control state is then broadcast to all devices to set the Full flags back to Empty, and the system is then ready for normal operation. 17 MU9C4320L ATMCAM XXXXXXXXH is written to have ...
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... MU9C4320L ATMCAM JTAG For detailed information on JTAG testing, refer to the IEEE Standard Test Access Port and Boundary-scan Architecture IEEE Std. 1149.1-1990 and 1149.1a-1993. The ATMCAM JTAG Instruction register is 3 bits long, giving eight possible JTAG instructions. The least significant bit is clocked in first. The JTAG instructions ...
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... RESERVED n/c AS RESERVED aaa AS RD VP@[AR] aaa AS RESERVED n/c NFD RESERVED n/c AS RESERVED All 1s AS RESERVED n/a = Not applicable n change NFA = Next Free address NFD = Highest-Priority device with a Free location S = Selected device 19 MU9C4320L ATMCAM PA:AA Scope aaa S aaa S aaa S aaa S HPMA HPD HPMA HPD n/c S n/c NFD n/c S n/c S n/c HPD/S ...
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... MU9C4320L ATMCAM CONTROL STATE DESCRIPTIONS Read/Write Memory Control State: Direct Write at Address Mnemonic: WR[aaa] Binary Op Code: aaa /W: LOW /AV: LOW PA:AA: aaa Description: Writes data from the DQ31–0 bus to the location defined by the address value present on the AC11–0 bus. The write optionally can be masked by the mask register selected through the Configuration register ...
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... HIGH. This value is the address of the location where a subsequent Write at Next Free Address cycle will be Scope: HPD written. The Page address of the device value is output on DQ15–12; DQ31–16 are LOW. 21 MU9C4320L ATMCAM Read Highest-Priority Matching Location RD[HPM] /AV: HIGH PA:AA: HPMA Scope: HPD ...
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... MU9C4320L ATMCAM Control State: Write Configuration Register Mnemonic: WR FR{MRnnn} Binary Op Code: XXX nnn 000 110 /W: LOW /AV: HIGH PA:AA: n/c Description: Writes data from the DQ31–0 bus to the Configuration register. The write is masked by the contents of Mask Register nnn. When nnn=000 no mask is used; when masking is selected, only bits in the addressed location that correspond to LOW values in the selected mask register are updated ...
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... Comparison cycle resulted in a multiple match. The /MF flag will go HIGH when all matches have been exhausted, therefore the scheme operates in vertically cascaded systems through the priority daisy chain. 23 MU9C4320L ATMCAM Compare Comparand Register with Memory Array CMP CR,{MRnnn} PA:AA: HPMA Scope: AS ...
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... MU9C4320L ATMCAM Set Validity Control State: Set Valid Indirect Mnemonic: SET V@[AR] Binary Op Code: XXX XXX 100 000 /W: LOW /AV: HIGH PA:AA: aaa Description: Set the Validity bit LOW at the location pointed to by the contents of the Address register. The location is set valid and will enter into comparisons during a Comparison cycle, and will not be written to during a Write at Next Free Address cycle ...
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... Reset State 0000 1111 0000 111111111111 Software Control Mode 1 = Not Low Priority CAM 1 = Disable VP Table 111111111111 1111 0000 1111 25 MU9C4320L ATMCAM Reset RST /AV: HIGH PA:AA: All ‘1’s Scope: AS Undefined Operations RESERVED Software Reset All locations set Empty No Change 00000000H 00000000H 00000000H ...
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... MU9C4320L ATMCAM Table 3: Configuration Register Bit Assignments Bit(s) Name 31:29 Direct Write Mask Source 28 Reserved 27:26 Control Mode 25 LPC 23:12 VP Table Address Mask 11:8 VP Table Page Address 7:4 Reserved 3:0 Page Address PA3-0 Table 4: Status Register Bit Assignments Bit(s) Name 31 /MV 30 /MF 29 /MM 28 /FF 27:26 Reserved ...
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... Others -2 2 Internal Pull-Ups -10 10 Max MU9C4320L ATMCAM Units Notes Volts Volts Volts Still air C Units Notes mA t ELEL = t ELEL (min.); HIGH Volts -2.0 mA Volts 4 GND Kohms ...
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... MU9C4320L ATMCAM Switching Test Figures Under T est Under T est INPUT WAVEFORM 50% AMPLITUDE 3.3 Vo lts R1 = 635 Device ( jig ) R2 = 702 o hm Figure 5: AC Test Load A 3.3 Vo lts R1 = 635 evice R2 = 702 o hm Figure 6: AC Test Load POIN T ...
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... MU9C4320L ATMCAM -90 - 120 ...
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... MU9C4320L ATMCAM TIMING DIAGRAMS /CS1 or 2 AC11-0 DQ31-0, /VB /CS1 or 2 AC1 1-0 DQ31 - / Figure 8: Read Cycle / / /FF Figure 9: Write Cycle 30 Timing Diagrams Rev. 3 ...
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... PA3– 0 :AA11–0 /MF, /MV, /MM /E /RESET TCLK TDI, TMS TDO Rev / / Figure 10: Compare Cycle Figure 11: Reset Cycle Figure 12: JTAG Test Cycle 31 MU9C4320L ATMCAM ...
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... MU9C4320L ATMCAM ORDERING INFORMATION Part Number Cycle Time MU9C4320L-70TDC 70ns MU9C4320L-90TDC 90ns MU9C4320L-12TDC 120ns MU9C4320L-70TDI 70ns MU9C4320L-90TDI 90ns MU9C4320L-12TDI 120ns PACKAGE 100-pin Dim. Dim. Dim. TQFP A1 A2 Min. 0.05 1.35 0.22 Max. 0.15 1.45 0.38 MUSIC Semiconductors’ agent or distributor: Worldwide Headquarters MUSIC Semiconductors 2290 N. First St., Suite 201 ...