ymf740c ETC-unknow, ymf740c Datasheet - Page 19

• Manufacturer Part Number: ymf740c
• Description: Ds-1l
• Manufacturer: ETC-unknow

YMF740C
48-49h: DS-1L Control Register
4A-4Bh: DS-1L Power Control Register
b0................CRST: AC’97 Software Reset Signal Control
b0................DMC: Disable Master Clock Oscillation
b1................DPLL0: Disable PLL0 Clock Oscillation
b2................DPLL1: Disable PLL1 Clock Oscillation
b3................PSL0: Power Save Legacy Audio Block 0
b4................PSL1: Power Save Legacy Audio Block 1
PR7
This bit controls the CRST# signal.
Setting this bit to “1” disables the oscillation of the Master Clock (24.576 MHz).
Setting this bit to “1” disables the oscillation of PLL for the Legacy Audio function.
Setting this bit to “1” disables the oscillation of PLL for the PCI Audio function.
Setting this bit to “1” stops providing the clock with the Legacy Audio function block 0. This block
includes FM Synthesizer and SB Pro engines.
Setting this bit to “1” stops providing the clock with the Legacy Audio function block 1. This block
includes MPU401 and Joystick.
b15
b15
“0”: Inactive (CRST#=High)
“1”: Active (CRST#=Low)
“0”: Normal
“1”: Disable
“0”: Normal
“1”: Disable
“0”: Normal
“1”: Disable
“0”: Normal
“1”: Power Save
“0”: Normal
“1”: Power Save
-
Read / Write
Default: 0001h
Access Bus Width: 8, 16, 32-bit
Read / Write
Default: 0000h
Access Bus Width: 8, 16, 32-bit
PR6
b14
b14
-
PR5
b13
b13
-
PR4
b12
b12
-
(default)
(default)
(default)
(default)
(default)
PR3
b11
b11
-
PR2
(default)
b10
b10
-
PR1
b9
b9
-
-19-
PR0
b8
b8
-
b7
b7
-
-
b6
b6
-
-
PSN
b5
b5
-
PSL1
b4
b4
-
PSL0 DPLL1 DPLL0 DMC
b3
b3
-
January 14, 1999
b2
b2
-
b1
b1
-
CRST
b0
b0