msm80c86a-10js Oki Semiconductor, msm80c86a-10js Datasheet - Page 24

• Manufacturer Part Number: msm80c86a-10js
• Description: 16-bit Cmos Microprocessor
• Manufacturer: Oki Semiconductor

¡ Semiconductor
MSM80C86A-10RS/GS/JS
Interrupt Acknowledge
During the interrupt acknowledge sequence, further interrupts are disabled. The interrupt
enable bit is reset by any interrupt, after which the Flag register is automatically pushed onto
the stack. During the acknowledge sequence, the CPU emits the lock signal from T2 of the first
bus cycle to T2 of the second bus cycle. At second bus cycles, byte is fetched from the external
device as a vector which identified the type of interrupt. This vector is multiplied by four and
used as a interrupt pointer address. (INTR only)
The interrupt Return (IRET) instruction includes a Flag pop operation which returns the
original interrupt enable bit when it restores the Flag.
HALT
When a Halt instruction is executed, the CPU enters the Halt state. An interrupt request or
RESET will force the MSM80C86A-10 out of the Halt state.
System Timing – Minimum Mode
A bus cycle begins T1 with an ALE signal. The trailing edge of ALE is used to latch the address.
From T1 to T4 the M/IO signal indicates a memory or I/O operation. From T2 to T4, the address
data bus changes the address but to data bus.
The read (RD), write (WR) and interrupt acknowledge (INTA) signals causes the addressed
device to enable data bus. These signal becomes active at the beginning of T2 and inactive at
the beginning of T4.
System Timing – Maximum Mode
At maximum mode, the MSM82C88-2 Bus Controller is added to system. The CPU sends status
information to the Bus Controller. Bus timing signals are generated by Bus Controller. Bus
timing is almost the same as in the minimum mode.
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