msm80c86a-10js Oki Semiconductor, msm80c86a-10js Datasheet - Page 21

• Manufacturer Part Number: msm80c86a-10js
• Description: 16-bit Cmos Microprocessor
• Manufacturer: Oki Semiconductor

¡ Semiconductor
Minimum and Maximum Modes
The MSM80C86A-10 has two system modes: minimum and maximum. When using maximum
mode, it is easy to organize a multi-CPU system with a MSM82C88-2 Bus Controller which
generates the bus control signal.
When using minimum mode, it is easy to organize a simple system by generating bus control
signal by itself.
MN/MX is the mode select pin. Definition of 24-31 pin changes depend on the MN/MX pin.
Bus Operation
The MSM80C86A-10 has a time multiplexed address and data bus. If a non-multiplexed bus is
desired for a system, it is only to add the address latch.
A CPU bus cycle consists of at least four clock cycles: T1, T2, T3 and T4. (Fig. 4)
The address output occurs during T1 and data transfer occurs during T3 and T4. T2 is used for
changing the direction of the bus at the read operation. When the device which is accessed by
the CPU is not ready for The data transfer and the CPU “NOT READY”, TW cycles are inserted
between T3 and T4.
When a bus cycle is not needed, T1 cycles are inserted between the bus cycles for internal
execution. During the T1 cycle, the ALE signal is output from the CPU or the MSM82C88-2
depending on MN/MX. At the trailing edge of ALE, a valid address may be latched.
Status bits S
type of bus operation according to the following table.
Status bits S
during T2 through T4.
S
following table.
I/O Addressing
The MSM80C86A-10 has 64 Kbytes of I/O or as 32 Kwords I/O. When the CPU accesses an I/
O device, addresses AD
low.
The I/O ports addresses are same as memory, so it is necessary to be careful when using 8-bit
peripherals.
0 (LOW)
0
0
0
1 (HIGH)
1
1
1
3
and S
S
2
4
S
indicate which segment register was selected on the bus cycle, according to the
0
0
1
1
0
0
1
1
1
0
3
, S
through S
1
and S
S
0
1
0
1
0
1
0
1
0
2
Interrupt acknowledge
Read I/O
Write I/O
Halt
Instruciton Fetch
Read Data from Memory
Write Data to Memory
Passive (no bus cycle)
0
are used in the maximum mode by the bus controller to recognize the
7
- AD
are multiplexed with A
Characteristics
15
are in the same format as a memory address, and A
S
16
0 (LOW)
0
1 (HIGH)
1
5
- A
indicates interrupt enable Flag.
S
4
19
, and BHE: therefore, they are valid
S
0
1
0
1
3
MSM80C86A-10RS/GS/JS
Alternate Data (Extra segment)
Stack
Code or None
Data
Characteristics
16
- A
21/37
19
are