msm80c86a-10js Oki Semiconductor, msm80c86a-10js Datasheet - Page 16

• Manufacturer Part Number: msm80c86a-10js
• Description: 16-bit Cmos Microprocessor
• Manufacturer: Oki Semiconductor

¡ Semiconductor
INTA
INTERRUPT ACKNOWLEDGE: Output
TEST
TEST: Input
NMI
NON MASKABLE INTERRUPT: Input
RESET
RESET:Input
CLK
CLOCK: Input
MN/MX
MINIMUM/MAXIMUM: Input
V
V
GND
GROUND
The following pin function descriptions are maximum mode only. Other pin functions are
already described.
S
STATUS: Output
CC
O
CC
This line is a read strobe signal for the interrupt acknowledge cycle. This line is active low.
This line is examined by the WAIT instruction.
When TEST is high, the CPU enters idle cycle.
When TEST is low, the CPU exits the idle cycle.
This line causes a type 2 interrupt.
NMI is not maskable.
This signal is internally synchronized and needs 2-clock cycles of pulse width.
This signal causes the CPU to initialize immediately.
This signal is active high and must be at least four clock cycles.
This signal provides the basic timing for the internal circuit.
This signal selects the CPU’s operating mode.
When V
These lines indicate bus status and they are used by the MSM82C88-2 Bus Controller to
generate all memory and I/O access control signals.
These lines are high impedance during hold acknowledge. These status lines are encoded as
shown.
When GND is connected, the CPU operates in Maximum mode.
, S
: +5V supplied.
1
, S
2
CC
is connected, the CPU operates in Minimum mode.
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