l033c12v Advanced Micro Devices, l033c12v Datasheet - Page 21

• Manufacturer Part Number: l033c12v
• Description: 32 Megabit 4 M X 8-bit Cmos 3.0 Volt-only Uniform Sector Flash Memory - Advanced Micro Devices
• Manufacturer: Advanced Micro Devices

quence, eliminating two cycles from the command se-
quence. In addition, the device uses the higher voltage
on the ACC pin to accelerate the operation. Note that
quence should be reinitiated once the device has reset
to reading array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may
halt the operation and set DQ5 to “1,” or cause the
Data# Polling algorithm to indicate the operation was
successful. However, a succeeding read will show that
the data is still “0”. Only erase operations can convert
a “0” to a “1”.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to pro-
gram bytes to the device faster than using the stan-
dard program command sequence. The unlock bypass
command sequence is initiated by first writing two un-
lock cycles. This is followed by a third write cycle con-
taining the unlock bypass command, 20h. The device
then enters the unlock bypass mode. A two-cycle un-
lock bypass program command sequence is all that is
required to program in this mode. The first cycle in this
sequence contains the unlock bypass program com-
mand, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total program-
ming time. Table 9 shows the requirements for the
command sequence.
During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the data
90h; the second cycle the data 00h. Addresses are
don’t cares for both cycles. The device then returns to
reading array data.
Accelerated Program Operations
The device offers accelerated program operations
through the ACC pin. When the system asserts V
the ACC pin, the device automatically enters the Un-
lock Bypass mode. The system may then write the
two-cycle Unlock Bypass program command se-
the ACC pin must not be at V
operations, or device damage may result . If ACC is to
be permanently set, it is recommended that it be tied
to V
Figure 3 illustrates the algorithm for the program oper-
ation. See the Erase/Program Operations table in “AC
Characteristics” for parameters, and to Figure 15 for
timing diagrams.
20
CC
to minimize current consumption.
HH
during read or erase
HH
Am29LV033C
on
Note: See Table 9 for program command sequence.
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 9 shows
the address and data requirements for the chip erase
command sequence.
Any commands written to the chip during the Embed-
ded Erase algorithm are ignored. Note that a hard-
w a r e r e s e t d u r i n g t h e c h i p e r a s e o p e r a t i o n
immediately terminates the operation. The Chip Erase
command sequence should be reinitiated once the de-
Increment Address
Figure 3. Program Operation
in progress
Embedded
algorithm
Program
No
Command Sequence
Write Program
Last Address?
Programming
from System
Verify Data?
Completed
Data Poll
START
Yes
Yes
No