m3819 Renesas Electronics Corporation., m3819 Datasheet - Page 11

• Manufacturer Part Number: m3819
• Description: Mitsubishi 8-bit Single-chip Microcomputer 740 Family / 38000 Series
• Manufacturer: Renesas Electronics Corporation.

Table of contents
Fig. 2.3.3 Structure of Serial I/O automatic transfer control register ............................................. 87
Fig. 2.3.4 Structure of Serial I/O 1 register ....................................................................................... 87
Fig. 2.3.5 Structure of Serial I/O automatic transfer interval register ............................................ 88
Fig. 2.3.6 Structure of Serial I/O 2 control register .......................................................................... 88
Fig. 2.3.7 Structure of Serial I/O 3 control register .......................................................................... 89
Fig. 2.3.8 Structure of Interrupt request register 1 ........................................................................... 89
Fig. 2.3.9 Structure of Interrupt control register 1 ............................................................................ 90
Fig. 2.3.10 Serial I/O connection examples (1) ................................................................................. 91
Fig. 2.3.11 Serial I/O connection examples (2) ................................................................................. 92
Fig. 2.3.12 Setting of Serial I/O mode ................................................................................................ 93
Fig. 2.3.13 Connection diagram [Output of serial data] ................................................................... 94
Fig. 2.3.14 Timing chart [Output of serial data] ................................................................................ 94
Fig. 2.3.15 Setting of related registers [Output of serial data] ........................................................ 95
Fig. 2.3.16 Setting of transmission data [Output of serial data] ..................................................... 95
Fig. 2.3.17 Control procedure [Output of serial data] ....................................................................... 96
Fig. 2.3.18 Connection diagram [Data transmission or reception using automatic transfer] ....... 97
Fig. 2.3.19 Timing chart [Data transmission or reception using automatic transfer] .................... 97
Fig. 2.3.20 Setting of related registers [Data transmission or reception using automatic transfer] ................ 98
Fig. 2.3.21 Setting of transmission data [Data transmission or reception using automatic transfer] ............. 99
Fig. 2.3.22 Control procedure [Data transmission or reception using automatic transfer] ............................... 100
Fig. 2.3.23 Connection diagram
Fig. 2.3.24 Timing chart [Cyclic transmission or reception of block data between microcomputers] ............... 102
Fig. 2.3.25 Setting of related registers
Fig. 2.3.26 Control in the master unit .............................................................................................. 103
Fig. 2.3.27 Control in the slave unit ................................................................................................. 104
Fig. 2.4.1 Structure of AD/DA control register ................................................................................ 105
Fig. 2.4.2 Structure of A-D conversion register .............................................................................. 105
Fig. 2.4.3 Structure of Interrupt request register 2 ........................................................................ 106
Fig. 2.4.4 Structure of Interrupt control register 2 ......................................................................... 106
Fig. 2.4.5 Connection diagram [Conversion of Analog input voltage] ......................................... 107
Fig. 2.4.6 Setting of related registers [Conversion of Analog input voltage] ............................. 107
Fig. 2.4.7 Control procedure [Conversion of Analog input voltage] ............................................. 108
Fig. 2.5.1 Structure of Port P0 segment/digit switch register ....................................................... 109
Fig. 2.5.2 Structure of Port P2 digit/port switch register ............................................................... 109
Fig. 2.5.3 Structure of Port P8 segment/port switch register ....................................................... 110
Fig. 2.5.4 Structure of Port PA segment/port switch register ....................................................... 110
Fig. 2.5.5 Structure of FLDC mode register 1 ................................................................................ 111
Fig. 2.5.6 Structure of FLDC mode register 2 ................................................................................ 112
Fig. 2.5.7 Structure of FLD data pointer ......................................................................................... 113
Fig. 2.5.8 Structure of FLD data pointer reload register ............................................................... 113
Fig. 2.5.9 Structure of Interrupt request register 2 ........................................................................ 114
Fig. 2.5.10 Structure of Interrupt control register 2 ....................................................................... 114
Fig. 2.5.11 Connection diagram [FLD automatic display and Key-scan using segment pin] ... 115
Fig. 2.5.12 Timing chart [FLD automatic display and Key-scan using segment pin] .............. 115
Fig. 2.5.13 Enlarged view of SEG
Fig. 2.5.14 Setting of related registers (1) [FLD automatic display and Key-scan using segment pin] .... 116
Fig. 2.5.15 Setting of related registers (2) [FLD automatic display and Key-scan using segment pin] .... 117
Fig. 2.5.16 Example of FLD digit allocation [FLD automatic display and Key-scan using segment pin] . 119
Fig. 2.5.17 Control procedure [FLD automatic display and Key-scan using segment pin] ...... 120
[Cyclic transmission or reception of block data between microcomputers] ........... 101
[Cyclic transmission or reception of block data between microcomputers] ........... 102
3819 Group USER’S MANUAL
24
to SEG
31
during Tscan ....................................................... 116
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