k4j55323qg Samsung Semiconductor, Inc., k4j55323qg Datasheet - Page 4

• Manufacturer Part Number: k4j55323qg
• Description: 256mbit Gddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

Note :
1. RFU1 is reserved for future use
2. RFU2 is reserved for future use
3. RFM : When the MF ball is tied LOW, RFM(H10) receiver is disabled and it recommended to be driven to a static LOW state, however,
Please refer to Mirror Function Signal Mapping table at page 6.
K4J55323QG
4.0 PIN CONFIGURATION
Normal Package (Top View)
either static HIGH or floating state on this pin will not cause any problem for the DRAM. When the MF ball is tied HIGH, RAS(H3)
becomes RFM due to mirror function and the receiver is disabled. It recommended to be driven to a static LOW state, however, either
static HIGH or floating state on this pin will not cause any problem for the DRAM
B
C
D
G
E
F
H
J
M
A
K
N
L
P
R
T
V
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VDDA
VSSQ
VSSQ
VREF
VSSA
VDD
VSS
VSS
VDD
1
WDQS0
WDQS3
VSSQ
VSSQ
RFU1
DQ24
DQ26
DQ28
DQ30
DQ0
VDD
DQ2
DQ4
DQ6
VDD
A10
A1
2
RDQS0
RDQS3
RFU2
DQ25
DQ27
DQ29
DQ31
DM0
VSS
DQ1
DQ3
DQ5
DQ7
RAS
DM3
VSS
3
A2
VSSQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
CAS
SEN
CKE
BA0
A11
ZQ
4
A0
A3
5
- 4 /53 -
6
7
8
RESET
VSSQ
VDDQ
VSSQ
VDDQ
VDDQ
VDDQ
VSSQ
VDDQ
VSSQ
BA1
MF
CS
WE
A4
A7
A9
9
RDQS1 WDQS1
RDQS2 WDQS2
DQ11
DQ13
DQ15
DQ17
DQ19
DQ21
DQ23
VSS
DQ9
RFM
DM1
DM2
VSS
10
CK
A6
256M GDDR3 SDRAM
A8/AP
VSSQ
VSSQ
DQ10
DQ12
DQ14
DQ16
DQ18
DQ20
DQ22
VDD
DQ8
VDD
CK
11
A5
Rev. 1.3 June 2006
VSSQ
VDDQ
VDDQ
VSSQ
VDDQ
VDDA
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
VREF
VSSA
VDD
VDD
VSS
VSS
12