pallv16v8-10 Lattice Semiconductor Corp., pallv16v8-10 Datasheet - Page 4

• Manufacturer Part Number: pallv16v8-10
• Description: Low Voltage, Zero Power 20-pin Ee Cmos Universal Programmable Array Logic
• Manufacturer: Lattice Semiconductor Corp.

SG0 replaces SG1 on the feedback multiplexer. This accommodates CLK being the adjacent pin for
MC
Registered Output Configuration
The control bit settings are SG0 = 0, SG1 = 1 and SL0
configuration. All eight product terms are available as inputs to the OR gate. Data polarity is
determined by SL1
path is from Q on the register. The output buffer is enabled by OE.
Combinatorial Configurations
The PALLV16V8 has three combinatorial output configurations: dedicated output in a non-
registered device, I/O in a non-registered device and I/O in a registered device.
Dedicated Output In a Non-Registered Device
The control bit settings are SG0 = 1, SG1 = 0 and SL0
the OR gate. Although the macrocell is a dedicated output, the feedback is used, with the exception
of MC
used in a non-registered device, pins 1 and 11 are available as input signals. Pin 1 will use the
feedback path of MC
Combinatorial I/O In a Non-Registered Device
The control bit settings are SG0 = 1, SG1 = 1, and SL0
to the OR gate. The eighth product term is used to enable the output buffer. The signal at the I/O
pin is fed back to the AND array via the feedback multiplexer. This allows the pin to be used as
an input.
Because CLK and OE are not used in a non-registered device, pins 1 and 11 are available as inputs.
Pin 1 will use the feedback path of MC
Combinatorial I/O in a Registered Device
The control bit settings are SG0 = 0, SG1 = 1 and SL0
to the OR gate. The eighth product term is used as the output enable. The feedback signal is the
corresponding I/O signal.
Dedicated Input Configuration
The control bit settings are SG0 = 1, SG1 = 0 and SL0
MC
pins 1 and 11. These configurations are summarized in Table 1 and illustrated in Figure 2.
4
7
0
and MC
and OE the adjacent pin for MC
3
and MC
7
, the feedback signal is an adjacent I/O. For MC
4
. MC
x
.
The flip-flop is loaded on the LOW-to-HIGH transition of CLK. The feedback
3
7
, and pin 11 will use the feedback path of MC
and MC
PALLV16V8-10 and PALLV16V8Z-20 Families
4
do not use feedback in this mode. Because CLK and OE are not
0
.
7
, and pin 11 will use the feedback path of MC
x
x
x
x
=1. The output buffer is disabled. Except for
x
=1. Only seven product terms are available
=0. All eight product terms are available to
=1. Only seven product terms are available
=0. There is only one registered
0
and MC
0
.
7
, the feedback signals are
0
.