pallv16v8-10 Lattice Semiconductor Corp., pallv16v8-10 Datasheet
pallv16v8-10
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pallv16v8-10 Summary of contents
Page 1
... FINAL PALLV16V8-10 and PALLV16V8Z-20 Low Voltage, Zero Power 20-Pin EE CMOS Universal Programmable Array Logic DISTINCTIVE CHARACTERISTICS Low-voltage operation, 3.3 V JEDEC compatible — +3 +3 Pin and function compatible with all 20-pin PAL Electrically-erasable CMOS technology provides reconfigurable logic and full testability Direct plug-in replacement for the PAL16R8 series Designed to interface with both 3 ...
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... The programmable functions on the PALLV16V8 are automatically configured from the user’s design specification. The design specification is processed by development software to verify the design and create a programming file. This file, once downloaded to a programmer, configures the device according to the user’s desired function. 2 PALLV16V8-10 and PALLV16V8Z-20 Families ...
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... The configuration bits work by acting as control inputs for the multiplexers in the macrocell. There are four multiplexers: a product term input, an enable select, an output select, and a feedback select multiplexer. SG1 and SL0 are the control signals for all four multiplexers PALLV16V8-10 and PALLV16V8Z-20 Families SL0 ...
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... The control bit settings are SG0 = 1, SG1 = 0 and SL0 MC and MC , the feedback signal is an adjacent I/O. For pins 1 and 11. These configurations are summarized in Table 1 and illustrated in Figure 2. 4 PALLV16V8-10 and PALLV16V8Z-20 Families . 0 =0. There is only one registered x =0. All eight product terms are available ...
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... It can also save “DeMorganizing” efforts. Selection is through a programmable bit SL1 of the AND/OR logic. The output is active high if SL1 PALLV16V8-10 and PALLV16V8Z-20 Families Table 1. Macrocell Configuration Devices Emulated ...
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... Notes: . Feedback is not available on pins 15 and 16 in the combinatorial output mode. . The dedicated-input configuration is not available on pins 15 and 16. Figure 2. Macrocell Configurations 6 PALLV16V8-10 and PALLV16V8Z-20 Families OE CLK b. Registered active high d. Combinatorial I/O active high Note 1 f. Combinatorial output active high g. Dedicated input ...
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... Programming and Erasing The PALLV16V8 can be programmed on standard logic programmers. It also may be erased to reset a previously configured device back to its unprogrammed state. Erasure is automatically performed by the programming hardware. No special erase operation is required. PALLV16V8-10 and PALLV16V8Z-20 Families 7 ...
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... This saving is greater at the higher frequencies. Further hints on minimizing power consumption can be found in a separate document entitled, Minimizing Power Consumption with Zero-Power PLDs. 8 PALLV16V8-10 and PALLV16V8Z-20 Families < 30 A). The outputs will maintain CC vs. frequency graph. CC ...
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... CLK PALLV16V8-10 and PALLV16V8Z-20 Families SL0 7 SG1 SL1 SL0 6 SG1 SL1 SL0 ...
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... GND 10 10 PALLV16V8-10 and PALLV16V8Z-20 Families CLK SL0 3 SG1 SL1 SL0 2 SG1 SL1 SL0 1 ...
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... OUT 0 Max (Note 3) OUT CC Outputs Open ( mA Max MHz (Note 4) OUT CC (or I and I ). OZL IL OZL vs. frequency graph for typical measurements. CC PALLV16V8-10 (Com’ Min Max Unit 2 0 0.4 V 0.2 V 2.0 5 µA –100 µA 10 µ ...
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... Test Condition 25° MHz V = 2.0 V OUT 1/( 1/( 1/( can be found using the following equation: CF PALLV16V8-10 (Com’l) Typ Unit -10 Min Max Unit 71.4 MHz 83.3 MHz 83.3 MHz ...
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... 0 Max (Note 3) OUT MHz Outputs Open ( mA) OUT V = Max MHz (Note MHz (or I and I ). OZL IH OZH vs. frequency graph for typical measurements. CC PALLV16V8Z-20 (Ind - + Min Max Unit 2 – 0 0.4 V 0.2 V 2.0 5 µ ...
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... MHz V = 2.0 V OUT Min 1/( 1/( 1/( 66 will typically be about 2 ns faster. PD can be found using the following equation: CF PALLV16V8Z-20 (Ind) Typ Unit -20 Max Unit MHz 50 MHz MHz ...
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... Clock width OE Output Notes 1.5 V for input signals and V /2 for output signals Input pulse amplitude 3 Input rise and fall times typical. PALLV16V8-10 and PALLV16V8Z-20 Families Input or Feedback Clock V TO Registered Output 17713D-7 Input Output ...
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... Z H: Open PZX Closed H Z: Open PXZ Closed 16 PALLV16V8-10 and PALLV16V8Z-20 Families INPUTS OUTPUTS Must be Will be Steady Steady May Will be Change Changing from from May Will be Change Changing from from Don’t Care, ...
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... Half of the available product terms were used for each macrocell. On any vector, half of the outputs were switching. By utilizing 50% of the device, a midpoint is defined for I to estimate the I requirements for a particular design. CC PALLV16V8-10 and PALLV16V8Z-20 Families Frequency (MHz ...
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... INPUT/OUTPUT EQUIVALENT SCHEMATICS V CC > ESD Protection and Clamping 5-V Protection 18 PALLV16V8-10 and PALLV16V8Z-20 Families Test Conditions Max Storage Temperature Max Operating Temperature Normal Programming Conditions V CC Programming Pins only Programming Voltage Overshoot ...
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... Parameter Symbol Parameter Descriptions t Power-Up Reset Time PR t Input or Feedback Setup Time S t Clock Width LOW WL 2.7 V Power Registered Output Clock PALLV16V8-10 and PALLV16V8Z-20 Families Min See Switching Characteristics Figure 3. Power-Up Reset Waveform can rise CC Max Unit 1000 ns V ...
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... Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package. Furthermore, tests on packages are performed in a constant temperature. Therefore, the measurements can only be used similar environment. 20 PALLV16V8-10 and PALLV16V8Z-20 Families Parameter Description 200 lfpm air 400 lfpm air 600 lfpm air 800 lfpm air measurement relative to a specifi ...
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... I I GND 10 11 OE/I 9 17713D-2 PIN DESIGNATIONS CLK = Clock GND = Ground I = Input I/O = Input/Output Connect V = Supply Voltage CC PALLV16V8-10 and PALLV16V8Z-20 Families PLCC ...
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... CC SPEED – – Valid Combinations PALLV16V8-10 PC, JC, SC PALLV16V8Z-20 PI PALLV16V8-10 and PALLV16V8Z-20 Families - OPERATING CONDITIONS C I PACKAGE TYPE Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Vantis sales offi ...