SI2414 SILABS [Silicon Laboratories], SI2414 Datasheet - Page 22

• Manufacturer Part Number: SI2414
• Manufacturer: SILABS [Silicon Laboratories]

Si2456/Si2433/Si2414
Clocking/Low Power Modes
The Si2456/33/14 contains an on-chip phase-locked
loop (PLL) and clock generation. Using either a single
crystal or master clock input, the Si2456/33/14 can
generate all the internal clocks required to support the
featured modem protocols. Either a 4.9152 MHz clock
(3.3 V max input—see Table 5 on page 8) on XTALI or a
4.9152 MHz (±100 ppm max) crystal across XTALI and
XTALO form the master clock for the ISOmodem. This
clock source is sent to an internal PLL that generates all
necessary internal system clocks including the DSP
clock. Figure 6 shows a block diagram of how the DSP
clock and the CLKOUT are derived.
The DSP clock is generated from the 78.6432 MHz
clock via the N1 clock divider. N1 is programmed
through U6E[1:0] (N1) and defaults to 2 giving a DSP
clock rate of 39.3216 MHz. This DSP clock rate is
necessary to run the Si2456/33/14 in all modes
described in the data sheet.
22
78.6432 MHz
PLL
Figure 6. DSP Clock Divider and CLKOUT Generation
N1 = 2, 2.5, 3, 4
1 < R1 < 31
÷ (R1 + 1)
÷ N1
Rev. 0.9
Using the S24 S-register, the Si2456/33/14 can be set
to automatically enter sleep mode after a pre-
programmed time of inactivity with either the DTE or the
remote modem. The sleep mode is entered after (S24)
seconds have passed since the TX FIFO has been
empty. The ISOmodem remains in the sleep state until
either a 1 to 0 transition on TXD (serial mode) or a 1 to 0
transition on CS (parallel mode) occurs.
Additionally, the Si2456/33/14 may be placed in a
complete powerdown mode or wake-on-ring mode.
Complete
U65[13] (PDN). Once the PDN bit is written, the Si2456/
33/14 completely powers down and can only be
powered back on via the RESET pin.
A 78.6432 MHz/(R1 + 1) clock is produced on the
CLKOUT pin that may be used as an external system
clock. R1 may be programmed via U5E to any value
between 1 and 31 (default value = 31).
÷ 8
powerdown
CLKOUT
SDSP
1
0
DSP Clock
is
accomplished
via