ST72F63 STMICROELECTRONICS [STMicroelectronics], ST72F63 Datasheet - Page 64

• Manufacturer Part Number: ST72F63
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST7263B
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
CONTROL REGISTER 2 (SCICR2)
Read/Write
Reset Value: 0000 0000 (00 h)
Bit 7 = TIE Transmitter interrupt enable .
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever
Bit 6 = TCIE Transmission complete interrupt ena-
ble
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TC=1 in
Bit 5 = RIE Receiver interrupt enable .
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever OR=1
Bit 4 = ILIE Idle line interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever IDLE=1
Bit 3 = TE Transmitter enable.
This bit enables the transmitter and assigns the
TDO pin to the alternate function. It is set and
cleared by software.
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TIE
TDRE=1 in the SCISR register
the SCISR register
or RDRF=1 in the SCISR register
in the SCISR register.
7
TCIE
RIE
ILIE
TE
RE
RWU
SBK
0
0: Transmitter is disabled
1: Transmitter is enabled
Note: During transmission, a “0” pulse on the TE
bit (“0” followed by “1”) sends a preamble after the
current word.
Caution: The TDO pin is free for general purpose
I/O only when the TE and RE bits are both cleared
(or if TE is never set).
Bit 2 = RE Receiver enable.
This bit enables the receiver. It is set and cleared
by software.
0: Receiver is disabled
1: Receiver is enabled and begins searching for a
Bit 1 = RWU Receiver wake-up.
This bit determines if the SCI is in mute mode or
not. It is set and cleared by software and can be
cleared by hardware when a wake-up sequence is
recognized.
0: Receiver in active mode
1: Receiver in mute mode
Note: Before selecting mute mode (setting the
RWU bit), the SCI must receive some data first,
otherwise it cannot function in mute mode with
wakeup by idle line detection.
Bit 0 = SBK Send break.
This bit set is used to send break characters. It is
set and cleared by software.
0: No break character is transmitted
1: Break characters are transmitted
Note: If the SBK bit is set to “1” and then to “0”, the
transmitter will send a BREAK word at the end of
the current word.
start bit