ST72F321 STMICROELECTRONICS [STMicroelectronics], ST72F321 Datasheet - Page 14

• Manufacturer Part Number: ST72F321
• Description: 64/44-PIN 8-BIT MCU WITH 32 TO 60K FLASH/ROM, ADC, FIVE TIMERS, SPI, SCI, I2C INTERFACE
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST72321
Table 2. Hardware Register Map
14/189
Address
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
0010h
0011h
0012h
0017h
0018h
0019h
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
to
Port A
Port B
Port D
Port E
Port F
FLASH
Port C
Block
SPI
ITC
I
2
C
2)
2)
2)
2)
2)
PADR
PADDR
PAOR
PBDR
PBDDR
PBOR
PCDR
PCDDR
PCOR
PDDR
PDDDR
PDOR
PEDR
PEDDR
PEOR
PFDR
PFDDR
PFOR
I2CCR
I2CSR1
I2CSR2
I2CCCR
I2COAR1
I2COAR2
I2CDR
SPIDR
SPICR
SPICSR
ISPR0
ISPR1
ISPR2
ISPR3
EICR
FCSR
Register
Label
Port A Data Register
Port A Data Direction Register
Port A Option Register
Port B Data Register
Port B Data Direction Register
Port B Option Register
Port C Data Register
Port C Data Direction Register
Port C Option Register
Port D Data Register
Port D Data Direction Register
Port D Option Register
Port E Data Register
Port E Data Direction Register
Port E Option Register
Port F Data Register
Port F Data Direction Register
Port F Option Register
I
I
I
I
I
I
I
SPI Data I/O Register
SPI Control Register
SPI Control/Status Register
Interrupt Software Priority Register 0
Interrupt Software Priority Register 1
Interrupt Software Priority Register 2
Interrupt Software Priority Register 3
External Interrupt Control Register
Flash Control/Status Register
2
2
2
2
2
2
2
C Control Register
C Status Register 1
C Status Register 2
C Clock Control Register
C Own Address Register 1
C Own Address Register2
C Data Register
Reserved Area (6 Bytes)
Reserved Area (2 Bytes)
Register Name
Status
Reset
00h
00h
00h
00h
00h
00h
FFh
FFh
FFh
FFh
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
xxh
0xh
00h
00h
1)
1)
1)
1)
1)
1)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Remarks
2)
2)