thc63lvd104s THine Electronics,Inc., thc63lvd104s Datasheet

no-image

thc63lvd104s

Manufacturer Part Number
thc63lvd104s
Description
112mhz 30bits Color Lvds Receiver
Manufacturer
THine Electronics,Inc.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
THC63LVD104S
Manufacturer:
THINE
Quantity:
5 530
Part Number:
THC63LVD104S
Manufacturer:
THLINE
Quantity:
796
Part Number:
THC63LVD104S
Manufacturer:
THINE
Quantity:
1 000
Part Number:
THC63LVD104S
Manufacturer:
THINE
Quantity:
1 000
Part Number:
THC63LVD104S
Manufacturer:
THINE
Quantity:
20 000
Block Diagram
General Description
The THC63LVD104S receiver is designed to support
pixel data transmission between Host and Flat Panel
Display from NTSC up to SXGA resolutions. The
THC63LVD104S converts the LVDS data streams back
into 35bits of CMOS/TTL data with rising edge or fall-
ing edge clock for convenient with a variety of LCD
panel controllers.At a transmit clock frequency of
112MHz, 30bits of RGB data and 5bits of timing and
control data (HSYNC,VSYNC,DE,CNTL1,CNTL2)
are transmitted at an effective rate of 784Mbps per
LVDS channel.Using a 112MHz clock, the data
throughput is 490Mbytes per second.
THC63LVD104S Rev.1.0
Copyright 2004 THine Electronics, Inc. All rights reserved
CMOS/TTL INPUT
LVDS INPUT
(8 to112MHz)
RCLK+/-
RE+/-
RA+/-
RB+/-
RD+/-
RC+/-
R/F
DK
PD
OE
112MHz 30Bits Color LVDS Receiver
THC63LVD104S
PLL
1
Features
Wide dot clock range: 8-112MHz suited for NTSC,
VGA, SVGA, XGA, and SXGA
PLL requires no external components
50% output clock duty cycle
TTL clock edge and position programmable(3 step)
Power down mode
Low power single 2.5V CMOS design
TQFP 64pin
Pin compatible with THC63LVD104A
Fail-safe for Open CLK Input
7
7
7
7
7
CMOS/TTL OUTPUT
RA6-RA0
RB6-RB0
RC6-RC0
RD6-RD0
RE6-RE0
CLKOUT
THine Electronics, Inc.

Related parts for thc63lvd104s

thc63lvd104s Summary of contents

Page 1

... The THC63LVD104S receiver is designed to support pixel data transmission between Host and Flat Panel Display from NTSC up to SXGA resolutions. The THC63LVD104S converts the LVDS data streams back into 35bits of CMOS/TTL data with rising edge or fall- ing edge clock for convenient with a variety of LCD panel controllers ...

Page 2

... THC63LVD104S Rev.1.0 Pin Out RA- 49 RA+ 50 RB- 51 RB+ 52 LVCC 53 RC- 54 RC+ 55 RCLK- 56 RCLK+ 57 LGND 58 RD- 59 RD+ 60 RE- 61 RE+ 62 PGND 63 PVCC 64 Copyright 2004 THine Electronics, Inc. All rights reserved RB6 CLKOUT GND RC0 RC1 ...

Page 3

... THC63LVD104S Rev.1.0 Pin Description Pin Name Pin No. RA+, RA- 50, 49 RB+, RB- 52, 51 RC+, RC- 55, 54 RD+, RD- 60, 59 RE+,RE- 62, 61 RCLK+, RCLK- 57, 56 RA6 ~ RA0 40,41,42,43,45,46,47 RB6 ~ RB0 32,33,34,35,36,38,39 RC6 ~ RC0 22,24,25,26,27,28,29 RD6 ~ RD0 14,15,17,18,19,20,21 RE6 ~ RE0 6,7,8,10,11,12, R/F 5 VCC 9,23,37,48 CLKOUT 31 GND 1,16,30,44 LVCC 53 LGND 58 PVCC 64 PGND 63 Copyright 2004 THine Electronics, Inc. All rights reserved ...

Page 4

... THC63LVD104S Rev.1.0 Pin Description (Continued Rxn Absolute Maximum Ratings Supply Voltage ( CMOS/TTL Input Voltage CMOS/TTL Output Voltage LVDS Receiver Input Voltage Output Current Junction Temperature Storage Temperature Range Resistance to soldering heat Maximum Power Dissipation @+25 Recommended Operating Conditions Parameter ...

Page 5

... THC63LVD104S Rev.1.0 Electrical Characteristics CMOS/TTL DC Specifications Symbol Parameter V High Level Input Voltage IH V Low Level Input Voltage IL V High Level Input Voltage IH3 V Middle Level Input Voltage IM3 V Low Level Input Voltage IL3 V High Level Output Voltage OH V Low Level Output Voltage ...

Page 6

... THC63LVD104S Rev.1.0 Electrical Characteristics Checker Pattern CLKOUT Rx0 Rx1 Rx2 Rx3 Rx4 Rx5 Rx6 x=A,B,C,D,E Copyright 2004 THine Electronics, Inc. All rights reserved (Continued) Fig2. Test Pattern 6 THine Electronics, Inc. ...

Page 7

... THC63LVD104S Rev.1.0 Switching Characteristics Symbol Parameter CLKOUT Period t RCP (Fig4) CLKOUT High Time t RCH (Fig4) CLKOUT Low Time t RCL (Fig4) t TTL Data Setup to CLKOUT RS t TTL Data Hold to CLKOUT RH TTL Low to High Transition Time t TLH (Fig 3) TTL High to Low Transition Time ...

Page 8

... THC63LVD104S Rev.1.0 AC Timing Diagrams TTL Output C =8pF L TTL Output Load Fig3. CMOS/TTL Output Load and Transition Time CLKOUT Fig4. CLKOUT Period and High/Low Time CLKOUT DK=L CLKOUT DK=M CLKOUT DK=H Rxn A,B,C,D 0~6 Fig5. CLKOUT Position and Setup/Hold Timing Copyright 2004 THine Electronics, Inc. All rights reserved ...

Page 9

... THC63LVD104S Rev.1.0 AC Timing Diagrams (Continued diff RCLK+ (Differential) RA3’ RA2’ RA1’ RA0’ RA+/- RB+/- RB3’ RB2’ RB1’ RB0’ RC+/- RC3’ RC2’ RC1’ RC0’ RD+/- RD3’ RD2’ RD1’ RD0’ ...

Page 10

... THC63LVD104S Rev.1.0 AC Timing Diagrams (Continued) RCLK+ CLKOUT R/F=L Note: 1) Vdiff = (RCLK+) - (RCLK-) Fig8. RCLK +/- to CLK OUT Delay Copyright 2004 THine Electronics, Inc. All rights reserved diff t RCD VCC diff THine Electronics, Inc. ...

Page 11

... THC63LVD104S Rev.1.0 Package INDEX Copyright 2004 THine Electronics, Inc. All rights reserved THine THC63LVD104S 11 UNITS: mm THine Electronics, Inc. ...

Page 12

... CAUSED ONLY BY THC63LVD104HS WITHOUT ANY ITEM NOT SOLD BY THINE AND/OR ANY USERS’ ACTION. THINE IS NOT RESPONSIBLE FOR PROBLEMS CAUSED BY SPECIFICATIONS SUP- PLIED BY USERS. THC63LVD104S is designed on the premise that it should be used for ordinary electronic devices. Therefore, it shall not be used for applications that require extremely high-reliability (space equipment, nuclear control equipment, medical equipment that affects people’ ...

Related keywords