thc63lvdm83d THine Electronics,Inc., thc63lvdm83d Datasheet

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thc63lvdm83d

Manufacturer Part Number
thc63lvdm83d
Description
Reduced Swing Lvds 24bit Color Host-lcd Panel Interface
Manufacturer
THine Electronics,Inc.
Datasheet

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THC63LVDM83D
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THC63LVDM83D
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THC63LVDM83D _Rev.1.0_E1
General Description
The THC63LVDM83D transmitter is designed to sup-
port pixel data transmission between Host and Flat
Panel Display from NTSC up to SXGA+ resolutions.
The THC63LVDM83D converts 28bits of CMOS/TTL
data into LVDS(Low Voltage Differential Signaling)
data stream. The transmitter can be programmed for ris-
ing edge or falling edge clocks through a dedicated pin.
At a transmit clock frequency of 135MHz, 24bits of
RGB data and 4bits of timing and control data
(HSYNC, VSYNC, CNTL1, CNTL2) are transmitted at
an effective rate of 945Mbps per LVDS channel.
Copyright 2007 THine Electronics, Inc. All rights reserved
Block Diagram
REDUCED SWING LVDS 24Bit COLOR HOST-LCD PANEL INTERFACE
TRANSMITTER
(8 to 135MHz)
THC63LVDM83D
CLKIN
CMOS/TTL
/PDWN
TD0-6
TA0-6
TB0-6
TC0-6
INPUTS
R/F
RS
7
7
7
7
THC63LVDM83D
PLL
1
Features
Wide dot clock range: 8-135MHz suited for NTSC,
VGA, SVGA, XGA,SXGA and SXGA+
PLL requires no external components
Supports spread spectrum clock generator
On chip jitter filtering
Clock edge selectable
Supports reduced swing LVDS for low EMI
Power down mode
Low power single 3.3V CMOS design
Low profile 56 Lead TSSOP Package
Pin compatible with THC63LVDM83C/83R(24bits)
8-135MHz
(LVDS)
(56-945Mbit/On Each
CLOCK
DATA
TA +/-
TB +/-
TC +/-
TD +/-
TCLK +/-
(LVDS)
LVDS Channel)
THine Electronics, Inc.

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thc63lvdm83d Summary of contents

Page 1

... THC63LVDM83D _Rev.1.0_E1 THC63LVDM83D REDUCED SWING LVDS 24Bit COLOR HOST-LCD PANEL INTERFACE General Description The THC63LVDM83D transmitter is designed to sup- port pixel data transmission between Host and Flat Panel Display from NTSC up to SXGA+ resolutions. The THC63LVDM83D converts 28bits of CMOS/TTL data into LVDS(Low Voltage Differential Signaling) data stream ...

Page 2

... THC63LVDM83D_Rev.1.0_E1 Pin Out Copyright 2007 THine Electronics, Inc. All rights reserved THC63LVDM83D TA4 2 55 TA3 TD1 3 54 TA5 TA2 4 53 TA6 GND 5 52 TA1 GND 6 51 TB0 TA0 7 50 TB1 TD0 8 49 TD2 LVDS GND 9 48 VCC TA TA+ ...

Page 3

... THC63LVDM83D_Rev.1.0_E1 Pin Description Pin Name Pin # TA+, TA- 47, 48 TB+, TB- 45, 46 TC+, TC- 41, 42 TD+, TD- 37, 38 TCLK+, TCLK- 39, 40 TA0 ~ TA6 51, 52, 54, 55, 56 TB0 ~ TB6 6, 7, 11, 12, 14, 15, 19 TC0 ~ TC6 20, 22, 23, 24, 27, 28, 30 TD0 ~ TD6 50 10, 16, 18, 25 /PDWN R/F 17 ...

Page 4

... THC63LVDM83D _Rev.1.0_E1 Absolute Maximum Ratings Supply Voltage ( CMOS/TTL Input Voltage CMOS/TTL Output Voltage LVDS Driver Output Voltage Output Current Junction Temperature Storage Temperature Range Resistance to soldering heat Maximum Power Dissipation @+25 1. “Absolute Maximum Ratings” are those valued beyond which the safety of the device can not be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of “ ...

Page 5

... THC63LVDM83D_Rev.1.0_E1 Electrical Characteristics CMOS/TTL DC Specifications Symbol Parameter V High Level Input Voltage IH V Low Level Input Voltage IL 1 Small Swing Voltage V DDQ V Input Reference Voltage REF Small Swing High Level Input Voltage Small Swing Low Level Input Voltage I Input Current ...

Page 6

... THC63LVDM83D_Rev.1.0_E1 Supply Current Symbol Parameter Transmitter Supply I TCCW Current Transmitter Power Down I TCCS Supply Current Worst Case Pattern CLKIN Tx0 Tx1 Tx2 Tx3 Tx4 Tx5 Tx6 x=A,B,C,D Copyright 2007 THine Electronics, Inc. All rights reserved V Condition(*) Ω RL=100 ,CL=5pF f=85MHz V =3.3V, RS=V ...

Page 7

... THC63LVDM83D_Rev.1.0_E1 Switching Characteristics Symbol Parameter t CLK IN Transition time TCIT t CLK IN Period TCP t CLK IN High Time TCH t CLK IN Low Time TCL t CLK IN to TCLK+/- Delay TCD t TTL Data Setup to CLK TTL Data Hold from CLK LVDS Transition Time LVT t Output Data Position0 (T=7 ...

Page 8

... THC63LVDM83D_Rev.1.0_E1 AC Timing Diagrams TTL Inputs CLK IN VCC/2 Tx0-Tx6 VCC/2 TCLK+ TCLK- Small Swing Inputs CLK DDQ Tx0-Tx6 V /2 DDQ TCLK+ TCLK- Copyright 2007 THine Electronics, Inc. All rights reserved t TCP t TCH VCC/2 VCC/2 t TCL VCC/2 t TCD Note: ...

Page 9

... THC63LVDM83D_Rev.1.0_E1 AC Timing Diagrams LVDS Output diff TCLK+/- (Differential) TA+/- TB+/- TC+/- TD+/- Previous Cycle t TOP1 t TOP0 t TOP6 t TOP5 t TOP4 t TOP3 t TOP2 Phase Lock Loop Set Time /PDWN VCC CLKIN TCLK+/- Copyright 2007 THine Electronics, Inc. All rights reserved TA6 TA5 TA4 ...

Page 10

... THC63LVDM83D_Rev.1.0_E1 Package 56 Lead Molded Thin Shrink Small Outline Package, JEDEC ± 8.1 0.1 4.05 Copyright 2007 THine Electronics, Inc. All rights reserved ± 14.0 0 0.50 TYP 0.20 TYP 10 Unit : millimeters 29 ± 6.1 0.1 28 (1.0) 1.2 MAX ± 0.10 0.05 THine Electronics, Inc. ...

Page 11

... Judgment on whether THC63LVDM83D comes under strategic products prescribed by the Foreign Exchange and Foreign Trade Control Law is the user’s responsibility. 8. This technical document was provisionally created during development of THC63LVDM83D, so there is a possibil- ity of differences between it and the product’s final specifications. When designing circuits using THC63LVDM83D, be sure to refer to the final technical documents ...

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