THC63LVD823 THine Electronics,Inc., THC63LVD823 Datasheet

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THC63LVD823

Manufacturer Part Number
THC63LVD823
Description
Manufacturer
THine Electronics,Inc.
Datasheet

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THC63LVD823_Rev2.0
General Description
The THC63LVD823 transmitter is designed to support
Single Link transmission between Host and Flat Panel
Display up to SXGA+ resolutions and Dual Link trans-
mission between Host and Flat Panel Display up to
UXGA resolutions.
The THC63LVD823 converts 48bits of CMOS/TTL
data into LVDS(Low Voltage Differential Signaling)
data stream. The transmitter can be programmed for ris-
ing edge or falling edge clocks through a dedicated pin.
In Single Link, the transmit clock frequency of
135MHz, 48bits of RGB data are transmitted at an
effective rate of 945Mbps per LVDS channel. Using a
135MHz clock, the data throughput is 472Mbytes per
second.
In Dual Link, the transmit clock frequency of 85MHz,
48bits of RGB data are transmitted at an effective rate
of 595Mbps per LVDS channel. Using a 85MHz clock,
the data throughput is 595Mbytes per second.
Block Diagram
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
Single(135MHz)/Dual(170MHz) Link LVDS Transmitter for SXGA/SXGA+/UXGA
TRANSMITTER CLOCK IN
1st DATA
2nd DATA
CMOS/TTL INPUT
(25 to 85MHz)
GREEN1
GREEN2
HSYNC
VSYNC
BLUE1
BLUE2
/PDWN
RED1
RED2
DE
R/F
8
8
8
8
8
8
THC63LVD823
PLL
8
8
8
Features
1
Wide dot clock range: 25-135MHz suited for VGA,
SVGA, XGA, SXGA, SXGA+ and UXGA
PLL requires No external components
Supports Dual Link, Dual-in (TTL)/Dual-out
(LVDS) pixel up to 170MHz dot clock for UXGA
Supports Single Link, Dual-in (TTL)/Single-out
(LVDS) pixel up to 135MHz dot clock for SXGA+
Supports Single Link, Single-in (TTL)/Single-out
(LVDS) pixel up to 85MHz dot clock for XGA
Clock edge selectable
Supports Reduced swing LVDS for Low EMI
Power down mode
Low power single 3.3V CMOS design
100pin TQFP
THC63LVDM83R compatible
LVDS OUTPUT
(25 to 135MHz)
(25 to 85MHz)
TA1 +/-
TB1 +/-
TC1 +/-
TD1 +/-
TCLK1 +/-
TA2 +/-
TB2 +/-
TC2 +/-
TD2 +/-
TCLK2 +/-
1st Link
2nd Link
THine Electronics, Inc.

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THC63LVD823 Summary of contents

Page 1

... THC63LVD823_Rev2.0 THC63LVD823 Single(135MHz)/Dual(170MHz) Link LVDS Transmitter for SXGA/SXGA+/UXGA General Description The THC63LVD823 transmitter is designed to support Single Link transmission between Host and Flat Panel Display up to SXGA+ resolutions and Dual Link trans- mission between Host and Flat Panel Display up to UXGA resolutions ...

Page 2

... THC63LVD823 _Rev2.0 Pin Out B15 76 77 B16 B17 78 R20 79 R21 80 R22 81 R23 82 R24 83 R25 84 R26 85 R27 86 VCC 87 GND 88 G20 89 G21 90 G22 91 G23 92 G24 93 G25 94 G26 95 G27 96 B20 97 B21 98 B22 99 B23 100 Copyright 2000-2003 THine Electronics, Inc. All rights reserved ...

Page 3

... THC63LVD823 _Rev2.0 Pin Description Pin Name Pin # TA1+, TA1- 48, 49 TB1+, TB1- 46, 47 TC1+, TC1- 43, 44 TD1+, TD1- 39, 40 TCLK1+, TCLK1- 41, 42 TA2+, TA2- 36, 37 TB2+, TB2- 34, 35 TC2+, TC2- 31, 32 TD2+, TD2- 27, 28 TCLK2+, TCLK2- 29, 30 60, 59, 58, 57, R17 ~ R10 ...

Page 4

... THC63LVD823 _Rev2.0 Pin Name Pin # R/F 11 VCC 3, 55, 71, 87 GND 4, 56, 72, 88 LVDS VCC 33, 45 LVDS GND 26, 38, 50 PLL VCC 24 PLL GND 23, 25 Absolute Maximum Ratings Supply Voltage ( CMOS/TTL Input Voltage CMOS/TTL Output Voltage LVDS Driver Output Voltage Output Current Junction Temperature ...

Page 5

... THC63LVD823 _Rev2.0 LVDS Transmitter DC Specifications Symbol Parameter VOD Differential Output Voltage Change in VOD between ∆VOD complementary output states VOC Common Mode Voltage Change in VOC between ∆VOC complementary output states I Output Short Circuit Current OS I Output TRI-State current OZ Supply Current Symbol Parameter ...

Page 6

... THC63LVD823 _Rev2.0 256 Gray Scale Pattern CLKIN Rx0/Gx0/Bx0 Rx1/Gx1/Bx1 Rx2/Gx2/Bx2 Rx3/Gx3/Bx3 Rx4/Gx4/Bx4 Rx5/Gx5/Bx5 Rx6/Gx6/Bx6 Rx7/Gx7/Bx7 x=1,2 DE Double Checker Pattern CLKIN R1n/G1n/B1n R2n/G2n/B2n n=0~7 DE Copyright 2000-2003 THine Electronics, Inc. All rights reserved 6 THine Electronics, Inc. ...

Page 7

... THC63LVD823 _Rev2.0 Switching Characteristics Symbol Parameter t CLK IN Transition time TCIT t CLK IN Period TCIP t CLK IN High Time TCH t CLK IN Low Time TCL t TTL Data Setup to CLK TTL Data Hold from CKL CLK OUT Period TCOP t LVDS Transition Time LVT t Output Data Position0 (t ...

Page 8

... THC63LVD823 _Rev2.0 AC Timing Diagrams TTL Inputs 2.0V CLK IN Hsync Vsync DE Rxn Gxn x = 1,2 Bxn n = 0~7 Phase Lock Loop Set Time VCC CLKIN /PDWN TCLKx+/- Copyright 2000-2003 THine Electronics, Inc. All rights reserved t t TCIP TCH 2.0V 2. 2.0V 0.8V 3.0V 2.0V t TPLL 8 t TCL R 0.8V 0.8V R 2.0V 0.8V V =0V diff THine Electronics, Inc. ...

Page 9

... THC63LVD823 _Rev2.0 Power Up Sequence Power Up Sequence must be Sequence1 or Sequence2. 1)Sequence1 VCC PVCC LVCC GND PD GND 1) t < 10msec > 2)Sequence2 VCC PVCC LVCC GND PD GND PD pin must be High after VCC voltage is 3.0V. Copyright 2000-2003 THine Electronics, Inc. All rights reserved t PW ...

Page 10

... THC63LVD823 _Rev2.0 AC Timing Diagrams LVDS Outputs Tyx+/- Tyx6 Tyx5 Tyx4 TCLKx 1 A,B,C,D TCLK1+ t CK12 TCLK2+ Copyright 2000-2003 THine Electronics, Inc. All rights reserved t TOP2 t TOP3 t TOP4 t TOP5 t TOP6 t TOP0 t TOP1 Tyx3 Tyx2 Tyx1 Tyx0 Tyx6 Tyx5 diff t TCOP diff ...

Page 11

... THC63LVD823 _Rev2.0 Pixel Map Table for Single/Dual Link 1st Pixel Data TFT Panel Data 823 TTL Input Pin 24Bit 18Bit LSB R10 - R11 - R12 R10 R13 R11 R14 R12 R15 R13 R16 R14 MSB R17 R15 LSB G10 - G11 - G12 G10 ...

Page 12

... THC63LVD823 _Rev2.0 823 TTL Data Input Timing for Single/Dual Link Example : SXGA+(1400 x 1050) HSYNC DE CLKIN R1x/G1x/B1x R2x/G2x/B2x n = 0~7 Copyright 2000-2003 THine Electronics, Inc. All rights reserved # 1395 #1397 # 1396 #1398 #1 #2 #1399 TFT Panel (1400 x 1050) 12 #1399 ...

Page 13

... THC63LVD823 _Rev2.0 TTL Data Inputs Timing Diagrams in Dual Link (Dual-in / Dual-out Mode) Previous Cycle TCLK1+ TA1+/- R16’ R15’ R14’ TB1+/- G17’ G16’ G15’ TC1+/- B17’ B16’ HSYNC’ TD1+/- B10’ G11’ ...

Page 14

... THC63LVD823 _Rev2.0 TTL Data Inputs Timing Diagrams in Single Link (Dual-in / Single-out Mode) Previous Cycle (2nd Pixel Data) TCLK1+ TA1+/- R26’ R25’ R24’ TB1+/- G27’ G26’ G25’ TC1+/- B27’ B26’ HSYNC’ TD1+/- B20’ ...

Page 15

... THC63LVD823 _Rev2.0 Package INDEX ∆ 100 PIN No.1 0.5TYP 0. Copyright 2000-2003 THine Electronics, Inc. All rights reserved UNIT:mm 15 THine Electronics, Inc. ...

Page 16

... Judgment on whether THC63LVD823 comes under strategic products prescribed by the Foreign Exchange and For- eign Trade Control Law is the user’s responsibility. 8. This technical document was provisionally created during development of THC63LVD823, so there is a possibility of differences between it and the product’s final specifications. When designing circuits using THC63LVD823, be sure to refer to the final technical documents ...

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