ST18-AU1 STMICROELECTRONICS [STMicroelectronics], ST18-AU1 Datasheet - Page 59

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ST18-AU1

Manufacturer Part Number
ST18-AU1
Description
SIX-CHANNEL DOLBY AC3/MPEG2 AUDIO DECODER
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
Data buses (XD/YD and XA/YA) are provided externally. Data memories (RAM, ROM) and
peripherals registers are mapped in these address spaces.
Instruction bus (ID/IA) gives access to program memory (RAM, ROM). Each bus has its own
control interface.
Table 16.1
Depending on the calculation mode, the D950Core DCU computes operands which can be
considered as 16 or 32-bit, signed or unsigned. It includes a 16 x 16-bit parallel multiplier able
to implement MAC-based functions in one cycle per MAC. A 40-bit arithmetic and logic unit,
including an 8-bit extension for arithmetic operations, implements a wide range of arithmetic
and logic functions. A 40-bit barrel shifter unit and a bit manipulation unit are included.
The tables below illustrate the different types of word length and word format available for
manipulation.
Table 16.2
39
XD
YD
ID
32
fractional
integer
Data/instruction bus
Data/instruction bus and corresponding address bus.
Summary of possible word lengths and formats
31
31
Bidirectional
Bidirectional
Bidirectional
Format
16
16
unsigned
unsigned
signed
signed
15
15
15
16-bit
16-bit
16-bit
7 0
XA
YA
0
0
0
0
IA
Minimum
- 32768
Corresponding address bus
1-bit word
8-bit word
16-bit word signed / unsigned
32-bit word signed / unsigned
40-bit word signed / unsigned
- 1
0
0
Unidirectional
Unidirectional
Unidirectional
+ 0.999969481
+ 0.99996948
Maximum
+ 32767
+ 65535
ST18-AU1
16-bit
16-bit
16-bit
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