ST18-AU1 STMICROELECTRONICS [STMicroelectronics], ST18-AU1 Datasheet
ST18-AU1
Related parts for ST18-AU1
ST18-AU1 Summary of contents
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... Dedicated hardware for emulation and test, IEEE 1149.1 (JTAG). 3.3V power supply, I/O’s 5V tolerant, 0.35 M HCMOS6 technology. 160 pin PQFP package February 98 This is preliminary information on a product in development or undergoing evaluation. Details are subject to change without notice. ST18-AU1 DMA Interrupt controller controller Clocks and timers ...
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INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Audio clock prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... I2S Data Input 18.3.11 I2S Data Input ST18-AU1 PACKAGE SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 19.1 ST18-AU1 PACKAGE PINOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 19.2 160 PIN PQFP PACKAGE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 20 DEVICE ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4/87 Table of Contents 4 ...
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... INTRODUCTION The ST18-AU1 is a single-chip multi-function audio processor for Dolby AC-3, MPEG-1/ MPEG-2 Layer-I/II audio encoded bitstreams, and DVD Linear PCM capable of decoding up to 5.1 channels of input Dolby AC-3 or MPEG-2 multi-channel encoded audio, and down mixing to 2 channels of PCM output audio. Maximum input data rates for Dolby AC-3 bitstream and MPEG-2 audio bitstream are 448 Kbits/s and 912 Kbits/s respectively ...
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... ST18-AU1 microcontroller is provided to allow ST18-AU1 operation control, bitstream information and internal status access. A typical DVD back-end system configuration is shown in Figure 1.1. Figure 1.1 Typical DVD back-end system configuration Video bitstream Control Compressed system input bitstreams System layer controller I Control 2 I Audio bitstream 6/87 DRAM ...
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... PIN DESCRIPTIONS The following tables detail the ST18-AU1 pin set. There is one table for each group of pins. The tables detail the pin name, type and a short description of the pin function. Signal names have a bar above if they are active low, otherwise they are active high. ...
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... ST18-AU1 Table 2.2 Direct X bus extension / Bus extension through bus switch unit (39 pins) Pin name Type Description ED0-15 I/O Bus switch unit (BSU) X/Y/I data extension bus. EA0-15 O BSU X/Y/I address extension bus. EIRD O BSU I-extension bus read strobe EIRD output. EIWR O BSU I-extension bus write strobe EIWR output. ...
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... When low, SCLK = output (internal audio master clock from clock prescaler) When high, SCLK = input (external audio master clock) 2 Table 2 Host interface (3 pins) Pin name Type Description 2 HDA I Data input/output (open drain output). 2 HCL / Clock input/output (open drain output). HSAS I Slave address select ST18-AU1 9/87 ...
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... ST18-AU1 Table 2.6 Data input 0 (4 pins) Pin name Type Description DIN0 I Serial data input CLKDIN0 I/O Data input clock Input in slave mode, output in master mode. WSDIN0 I/O Data input word select Input in slave mode, output in master mode. DREQ0 O Request for data input. Active low. ...
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... Asserted high when executing an instruction if Snapshot mode is enabled. Table 2.13 JTAG IEEE 1149.1 test access port(5 pins) Pin name Type Description TDI I Test data input. TCK I Test clock. TMS I Test mode select. TDO O Test data output. TRST I Test logic reset (also used for Emulator module). Active low. ST18-AU1 11/87 ...
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... ST18-AU1 3 FUNCTIONAL OVERVIEW A functional block diagram of the ST18-AU1 is shown in Figure 3.1. The modules that comprise the ST18-AU1 are outlined below and more detailed information is given in the following chapters of this datasheet. The interconnection of these blocks and all external interfaces are shown in the block diagram in Figure 3.2. ...
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... Figure 3.2 ST18-AU1 block diagram ST18-AU1 Interrupt IRQ controller Clocks and Clocks timers (13 pins) HCL Host HDA interface HSAS host interface) DIN 2 WSDIN Input serial CLKDIN interfaces DREQ PCM_OUT Host interface 2 The I C serial bus interface operated in slave mode enables connection to an external host processor ...
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... They provide the serial to parallel conversion and transfer the input data to the input buffer for further processing. Output serial interface The ST18-AU1 has three output serial interfaces. The output serial interfaces organize the PCM audio output into the required I IEC-958 transmitter ...
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... In addition kHz System Time Clock (STC) is provided to assist audio/video synchronization in systems which include a video decoder. Emulation unit and JTAG IEEE 1149.1 test access port The emulation unit (EMU) performs functions dedicated to emulation and test through the external IEEE 1149.1 JTAG interface. ST18-AU1 15/87 ...
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... ST18-AU1 4 HOST INTERFACE 2 The host interface is a fast I connection to an external host processor. It receives operating commands, and returns host requested bitstream information and internal status. 4.1 Host interface registers HSER: Host serial shift register This 16-bit shift register is used for serial data input and output. Data is shifted MSB first not visible from the D950 ...
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... ACKOFF Acknowledge generation disable 0 acknowledge enabled 1 acknowledge disabled 2 1 lsb ack msb byte 1 ..... HSER HDA lsb msb HDR byte 1 byte 0 (lsb) 8-bit (msb) YD (8-bit words HTIEN - - - EN ST18-AU1 2 1 lsb lsb 8-bit ACK- WS HEN OFF 17/87 ...
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... ST18-AU1 HTIEN Transfer interrupt enable 0 transfer interrupt disabled 1 transfer interrupt enabled STOPIEN Stop interrupt enable 0 stop interrupt disabled 1 stop interrupt enabled ACKFIEN Acknowledge fail interrupt 0 acknowledge fail interrupt disabled 1 acknowledge fail interrupt enabled BERRIEN Bus error interrupt 0 bus error interrupt disabled ...
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... Slave address bit 2 HSA3 Slave address bit 3 HSA4 Slave address bit 4 HSA5 Slave address bit 5 HSA6 Slave address bit 6 HSA7 Slave address bit 7 - RESERVED, read as 0. 4.2 List of host commands A list of host commands is given below ST18-AU1 19/87 ...
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... ST18-AU1 Table 4.1 Write commands Mnemonic Opcode HostInputMode 00 HostInputStrmFormat 01 HostOpmode 02 HostMute 03 HostAudiStrmIdSel 04 HostOutputChanConf 05 HostDualMonoReproMode 06 20/87 Size Command description and Parameter values (bits) 8 Input mode (type of bitstream). AC3 (default) MPEG -1 MPEG-2 MPEG-2 with extension PCM by pass Linear PCM 8 Input Stream Format ES (Default) DVD/PES 8 Operating Mode ...
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... Delay between the decoder and the bitstream sent via the SPDIF output. The delay is expressed in multiples of 1/Fs, where Fs is the sample frequency. The delay is signed. 0xffff to 0x7ffff (default SPDIF SMPTE Frame Rate Code not indicated 24/1001 24 25 30/1001 (default 60/1001 60 ST18-AU1 ...
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... ST18-AU1 Table 4.1 Write commands Mnemonic Opcode HostLpcmMixAlpha0-7 0F-16 HostLpcmMixBeta0-7 17-1E HostErrorConcealMod 1F HostLowPower 20 HostSerialInputCtrl 21 HostSerialInoutDiv 22 HostSerialOutputCtrl 23 HostSerialOutputDiv 24 HostAudioClockSel 25 HostSamplFreq 26 HostPcmNbBits 27 WriteStc 80 22/87 Size Command description and Parameter values (bits) 16 Linear PCM Downmixing Coefficients In LPCM mode: Alphai is the coefficient to downmix the channel i into the Left channel. Betai is the downmixing coefficient for channel i into the Right channel ...
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... Decoder errors Crc 8 Input Sampling Frequency Sampling frequency specified by the bitstream. For AC-3 fscod is returned. 8 Input Data Rate Data rate specified by the bitstream. For AC-3 frmsizecod is returned. 8 InputMultiChannelMode For AC-3 acmod is returned. 8 Karaoke Bitstream Non Karaoke Karaoke ST18-AU1 ...
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... ST18-AU1 Table 4.2 Read commands Mnemonic Opcode HostLfePresent 4B HodtCopyProtect 4C HostOpModeOut 4D HostInputBitstrmStatus 4E STC 81 PTS 82 24/87 Size Command description and parameter value (bits) 8 Lfe Present Lfe not present Lfe present 8 Copy Protected Not protected Protected 8 Operating Mode Idle Synchronising Decoding 8 Input Bitstream Status Idle Searching for PES sync word ...
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... INPUT SERIAL INTERFACE The ST18-AU1 has two input serial interfaces (DIN0 and DIN1). The interfaces are multi- format serial interfaces for inputting audio bitstreams. Supported formats include delayed 2 (I S)/non-delayed, left/right justified, 16/18/20/24-bit word, polarity options in L/R clock and input clock, and master/slave mode. They provide the serial to parallel conversion and transfer the input data to the input buffer for further processing ...
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... ST18-AU1 Justified If number of Clk cycles between WS transitions is > word size) 0 start justified: n bits read, starting from first bit: just after WS transition if Delayed =’0’ with 1 clk cycle delay after WS transition if Delayed=’1’ 1 end justified, end bit beein last bit received: just before WS transition if Delayed =’ ...
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... DREQ is asserted high when FIFO is full (if DREQ_EN=1) DIN0_IEN DIN0 interrupt enable 0 interrupt disabled 1’ interrupt enabled (when FIFO_THS = 1) CLR_Form Set formatter empty (active only at write time of FIFOCR) - RESERVED, read DREQ_ FIFO_level N SEL ST18-AU1 DMA_ DREQ - mod _EN 27/87 ...
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... ST18-AU1 FIFOSR: Input FIFO status register FIFO_FULL and FIFO_THR are cleared on reset Form_e PDC_N mpty ULL Bit Function FIFO_FULL FIFO full: set and reset by hardware FIFO_EMPTY FIFO empty: set and reset by hardware FIFO_THR FIFO threshold: set and reset by hardware ...
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... BUFCR: Buffer control register All bits are cleared on reset UDF_OUT BUF_IEN Bit Function EN_BUF Enable input/output buffer logic OVF_INBUF Input buffer overflow OVF_INB - - - UF_IEN INBUFOVF= ‘0’ INBUFOVF=INBUF_FULL ST18-AU1 UDF_ OVF_IN EN_B mod BUF UF 29/87 ...
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... ST18-AU1 UDF_mod Output buffer underflow 0 1 OVF_INBUF_IEN Input buffer overflow interrupt enable 0 1 UDF_OUTBUF_IEN Output buffer underflow interrupt enable RESERVED, Read as 0. BUFSR: Buffer status register All bits are cleared on reset Bit Function INBUF_FULL Input buffer full. Set and reset by hardware. ...
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... LSB on bits left justified. channel 1 LSB on bits left justified. Figure 7.1 PCMPR register example for 18-bit data words t Bit15 ch2 PCMPR00 17 16......... ch1 PCMPR01 17 16......... ch1 PCMPR02 1 0 Bit8 Bit7 ch2 unused unused 1 0 ST18-AU1 2 S serial format Bit0 ch2 ..... 2 ch1 ..... ..2 31/87 ...
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... ST18-AU1 PCMCR: Data in control register All bits are cleared on reset Mute play mute PCM _en Bit Function PCMEN PCM output enable 0 disable 1 enable WS Output word size bit 1 bit CLK_pol Clock pol 0 data and WS change on SCLKPCM falling edge ...
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... PCMDIV /= ‘00000 PCMCLK - RESERVED, read DMA req. serial out = 0 SCLK, WS not running no DMA req. serial out = 0 SCLK, WS running DMA req. serial out = ’data’ SCLK, WS running DMA req. serial out = 0 SCLK, WS running ... 510 ST18-AU1 PCMDIV 33/87 ...
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... ST18-AU1 8 INTERRUPT CONTROLLER The interrupt controller (ITC) manages the interrupts from the clocks and timers unit, the host interface, and the external interrupt for the DSP core. The interrupt controller also manages input/output buffer overflow/underflow interrupts. The interrupt controller has the following features: ...
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... SPL4 (2:0) SPL3 (2: ITACK EOI INTERRUPT CONTROLLER YWR YRD PERIPHERAL CLK RESET SPL2 (2:0) SPL1 (2:0) ST18-AU1 AS-DSP YD YA ITRQ0 ITRQ1 ITRQ2 ITRQ3 ITRQ4 ITRQ5 ITRQ6 ITRQ7 VR02020C CPL (2:0) 35/87 ...
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... ST18-AU1 Bit Function CPL Current priority level (- (default is 011) ES Empty stack flag 0: stack is used 1: stack is not used (default) SPL1 3-bit 1st stacked priority level SPL2 3-bit 2nd stacked priority level SPL3 3-bit 3rd stacked priority level SPL4 3-bit 4th stacked priority level The current priority levels available are shown below ...
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... PROGRAM IT2 IT3 SPL4 SPL3 SPL2 SPL1 ES CPL ISP IS4 IM4 IS3 IM3 IS2 IM2 ST18-AU1 INTERRUPT LEVEL 3 PROGRAM IT3 SPL4 SPL3 SPL2 SPL1 ES CPL ISP 2 VR02020D IS1 IM1 IS0 IM0 ...
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... ST18-AU1 IPR: Interrupt priority register (Address = 002A, Reset = 0000h, Read/Write IP7(1:0) IP6(1:0) IP5(1:0) Bit Function IP Interrupt priority level ( (default is 0) The IPR register contains the priority level of each ITRQ0-7 interrupt input. IP0-7 priority level is coded using two bits. The different values of IP are lowest priority, 3 highest priority) ...
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... When only some pending interrupt requests need to be acknowledged, the IPE bits of the other interrupt inputs must be reset. When the IPE bit is set by a direct register write an interrupt request will be generated irrespective of the state of the ITRQ pin. When the mask (IM) bit is set, the corresponding IPE bit is reset. ST18-AU1 39/87 ...
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... ST18-AU1 9 DMA CONTROLLER The DMA controller manages data transfer between memories and external peripherals and has the following features: four independent DMA channels transfers spaces (simultaneous transfers on X and Y spaces) cycle stealing operation: 3 cycles for a single data transfer (+1 cycle for transfers on I space) ...
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... DCC0-3: current count. This register contains the remaining number of transfers required to fill the entire block decremented after each transfer. The DCC values are: Reset DLA DCC DCC DCA(n+ DCA( DIC ST18-AU1 DCA(n+1) 0 DCA(n) DCA( DCA( DIA 0 41/87 ...
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... ST18-AU1 9.2.3 Control registers Three 16-bit control registers are dedicated to the DMA controller interface. These are the general control register, the address interrupt control register and the mask sensitivity control register. They are detailed below. DGC: General control register Three bits are dedicated for each DMA channel (bits channel 0, bits channel 1, bits channel 2, bits channel 3) ...
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... Reset = x3333h, Read/Write DSE3 DMK3 - - Bit Function DMKi DMA mask 0: DMA channel not masked 1: DMA channel masked (default) DSEi DMA sensitivity 0: Low level 1: Falling edge (default DSE2 DMK2 - - DSE1 DMK1 ST18-AU1 DSE0 DMK0 43/87 ...
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... ST18-AU1 10 IEC-958 TRANSMITTER The IEC-958 transmitter accepts either the AC-3/MPEG bitstream or the decoded audio output PCM data, and formats the input in accordance with the IEC-958 (S/PDIF) specification for output via the SPDIFOUT pin. For further information refer to the IEC-958 interface specification. ...
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... SPDIFPR0-2: 3x 16-bit SPDIF parallel registers The SPDIFPR0-2 registers are 16 bit SPDIF parallel registers used for intermediate storage of data. They are write only registers. disabled enabled bit 0 word size 0 16 bit 1 18 bit 0 20 bit 1 24 bit Y (input buffer) X (output buffer) valid defective ST18-AU1 45/87 ...
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... ST18-AU1 11 MEMORY 11.1 Internal memory resource One 8 Kword and two 16 Kword single port memories are included on-chip: Instruction memory on I space from address 0 to 16382 (16 K) X-Data memory on X space from address 0 to 16382 (16 K) Y-Data memory on Y space from address 256 to 8192 Note: the first 256 addresses of the Y space are reserved for the D950 memory-mapped registers and for on-chip memory mapped peripherals ...
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... Direct bus extension or bus extension through the BSU is controlled by setting the X-bus related BSU registers. 11.4 Y-memory bus extension through BSU The internal program memory is used from address 256 to 8192. Y-memory bus extension must be through the BSU controlled by setting the Y-bus related BSU registers. ST18-AU1 47/87 ...
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... ST18-AU1 12 BUS SWITCH UNIT The bus switch unit (BSU bi-directional switcher. It switches the 3 internal buses (I, X and Y) to the external (E) bus. 12.1 BSU control registers The BSU is programmable via six control registers mapped in the Y-memory space. These define the type of memory used, internal to external boundary address crossing, exchange type (external direct or through the BSU) and software wait-states count ...
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... IM EN_I - - - XA15 XA14 XA13 XA12 XA11 XA10 YA15 YA14 YA13 YA12 YA11 YA10 IA15 IA14 IA13 IA12 IA11 IA10 ST18-AU1 ...
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... ST18-AU1 Bit Function W3:0 Wait state count (1 to 16) for off-chip access (I-memory space) IA15:10 I-memory space map for boundary on-chip or off-chip EN_I Enable for I-space data exchanges IM Intel/Motorola 0: Motorola type for memories 1: Intel type for memories (default) ead 0, write don’t care. ...
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... The programmable prescaler and clock dividers of Data Input and PCM Output interfaces are used for the generation of data bit clocks. The prescaler divide range 510 defined by the content of the PSCTR register. Its output SCLKINT is a 50% duty cycle signal. ST18-AU1 51/87 ...
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... ST18-AU1 13.2 Clocks and timers registers PSCTR register Bit Function SCLKINT- SCLKINTDIV prescaler divide factor DIV 00000000 00000001 ... 11111111 fpll2 f = /2(SCLKINTDIV) if SCLKINTDIV /= 00000000 SCLKINT CLK_sel1 PCM output clock select: 0 Hardware (MCLK_MODE pin) 1 Software (according to bit 9) CLK_sel2 PCM Output Clock select: ...
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... An interrupt request is generated when the BLKCLKTR register is decremented to 0 and it is reset to its initial value. SPDIF Timer register input = FS (Samples Frequency) output = SPDIF_IRQ The SPDIFTR register is a 16-bit decrementer. It can be initialized to any value by the D950. An interrupt request is generated when it is decremented to 0 and reset to its initial value. ST18-AU1 53/87 ...
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... ST18-AU1 Figure 13.1 Clocks and timers block diagram Div 300 EXTAL0 (27 MHz) AUDIOCLK SCLK (in/out) MCLK_MODE FS 54/87 STC (32 bit counter) PSC (8-bit prescaler). PCM_OUT timer (16-bit). SPDIF timer (16-bit). D950 Y-bus (SCLKINT) MCLK_PCM mux MCLK_DIN BLKCLK_IRQ SPDIF_IRQ ...
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... Capture-IR state. There are three defined public instructions, see Table 14.1. All other instruction codes are reserved. Table 14.1 Instruction codes 1) Instruction code 04h 08h FFh 1) MSB... LSB; LSB closest to TDO Instruction Selected register IDCODE Identification EMU D950 IOscan BYPASS Bypass ST18-AU1 55/87 ...
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... ST18-AU1 15 EMULATION UNIT The emulation unit (EMU) performs functions dedicated to emulation and test through the external IEEE 1149.1 JTAG interface. Refer to Chapter 14 for details on the JTAG test access port. The emulation and test operations are controlled by the JTAG Test Access Port (TAP) and the emulator by means of dedicated control I/Os ...
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... TAP The emulation controller interface (see Table 2.12 and Table 2.13 on page 11) includes pins of different types: ERQ, IDLE and SNAP are used by the emulator tools. HALTACK indicates that the processor is halted in emulation mode. Comparators IA Control PC trace Logic ERQ, IDLE, SNAP ST18-AU1 57/87 ...
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... ST18-AU1 16 D950Core The D950Core is composed of three main units. Data Calculation Unit (DCU) Address Calculation Unit (ACU) Program Control Unit (PCU) For full details of the D950 DSP core refer to the D950Core datasheet ( document number 42- 1709 ). These units are organized in an HARVARD architecture around three bidirectional 16-bit buses, two for data and one for instruction ...
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... Corresponding address bus 16-bit XA Unidirectional 16-bit YA Unidirectional 16-bit IA Unidirectional 0 1-bit word 7 0 8-bit word 15 0 16-bit word signed / unsigned 15 0 32-bit word signed / unsigned 15 0 40-bit word signed / unsigned Minimum signed - 1 0 signed - 32768 0 ST18-AU1 16-bit 16-bit 16-bit Maximum + 0.999969481 + 0.99996948 + 32767 + 65535 59/87 ...
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... ST18-AU1 16.1 D950Core registers Register Function BX Modulo base address for X-memory space MX Modulo maximum address for X-memory space BY Modulo base address for Y-memory space MY Modulo maximum address for Y-memory space POR Port Output Register - 8LSB are significant, 8MSB are undefined when reading ...
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... Y SPACE MEMORY MAPPING 17.1 Memory map Figure 17.1 ST18-AU1 memory mapping RESERVED Internal Y RAM RESERVED Clocks and timers RESERVED S/PDIF RESERVED PCM output RESERVED Input/output buffer RESERVED Serial input 1 Serial input 0 RESERVED Host interface RESERVED ST18-AU1 FFFF 2000 1FFF 0100 00FF 00B5 ...
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... ST18-AU1 Bus switch unit RESERVED PLL RESERVED DMA controller RESERVED Interrupt controller RESERVED Emulator peripheral D950 core 17.2 Clocks and timers registers Address (Hex) Register 00B0 PSCTR 00B1 STCLTR 00B2 STCMTR 00B3 BLKCLKTR 00B4 SPDIFTR 62/87 0055 0050 004F 004A 0049 0048 0047 ...
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... PCM Output Data 01 PCM Output Data 02 PCM Output Data 10 PCM Output Data 11 PCM Output Data 12 PCM Output Data 20 PCM Output Data 21 PCM Output Data 22 PCM Output Clock divide factor Description In/Out Buffer Control In/Out Buffer Status Input Buffer Read Address ST18-AU1 63/87 ...
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... ST18-AU1 17.6 Serial input 1 registers Address (Hex) Register 0078 DIN1CR 0079 DIN1DIV 007A DIN1DR 17.7 Serial input 0 registers Address (Hex) Register 0070 DIN0CR 0071 DIN0DIV 0072 FIFOCR 0073 FIFOSR 0074 FIFOOut 0075 FORM 0076 PDCR 17.8 Host interface registers Address (Hex) Register 0060 HCR ...
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... DMA channel 1 initial count DMA channel 0 initial count DMA channel 3 current address DMA channel 2 current address DMA channel 1 current address DMA channel 0 current address DMA channel 3 initial address DMA channel 2 initial address DMA channel 1initial address DMA channel 0 initial address ST18-AU1 65/87 ...
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... ST18-AU1 17.12 Interrupt controller registers 002C ISR 002B ISPR 002A IPR 0029 IMR 0028 ICR 0027 IV7 0026 IV6 0025 IV5 0024 IV4 0023 IV3 0022 IV2 0021 IV1 0020 IV0 17.13 D950 core control registers Address (Hex) Register 0007 PCSR 0006 PCDR ...
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... On chip X RAM (16K words). to 3FFF Y Memory mapping address Name Function (Hex) 007F On chip Y RAM (7936 words). to Addresses (256 words) reserved for D950 and peripherals 1FFF memory mapped registers. I Memory mapping I address Name Function (Hex) 0000 On chip I RAM (16K words) to 3FFF ST18-AU1 67/87 ...
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... ST18-AU1 18 ELECTRICAL SPECIFICATIONS In the following tables TBD indicates ‘to be defined’. 18.1 DC Absolute maximum ratings Table 18.1 DC absolute maximum ratings Symbol Parameter VDD Power supply voltage Vin Input voltage Ta Operating temperature range Tstg Storage temperature range 18.2 DC Electrical characteristics Table 18.2 DC electrical characteristics Symbol Parameter ...
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... AC characteristics The following timings are based on simulations and may change when full characterisation is completed. Figure 18.1 Input waveforms 2.7v 1.5v 10% 0.3v r 90% 90% timing reference points ST18-AU1 2.5ns 1.5v 10% f 69/87 ...
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... ST18-AU1 Figure 18.2 Output load circuit and waveform From output under test CL = 50pF VOH VOL Table 18.3 AC measurement conditions - input only or output only pins VDDmin 0.3v 2.7v VDDmax 0.3v 2.7v 70/87 ~ IOL = 1mA IOH = 1mA 1.5v timing reference points 1.5V 1.5V 1.5V 1.5V Vref 1. 1mA 1mA ...
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... Vref Vref - 0.1V VOL For timing purposes a pin is no longer floating when a 100mV change from Vref occurs, but begins to float when a 150mV change from the loaded VOH/VOL level occurs. ~ IOL = 8mA Vref IOH = 8mA timing reference points ST18-AU1 VOH - 0.15v VOL - 0.15v 71/87 ...
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... ST18-AU1 18.3.1 Clocks electrical characteristics CLK0 t2 CLKOUT INCYCLE CLK1 t8 SCLK(out) No Parameter t1 CLKOUT rise time t2 CLKOUT fall time t3 CLKOUT high delay(1) t4 CLKOUT low delay(1) t5 INCYCLE high delay t6 INCYCLE low delay t7 SCLK out rise time t8 SCLK out fall time t9 SCLK out high delay(2) t9 SCLK out high delay(3) ...
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... IWRE high delay t17 IAE valid delay t18 IAE hold time t19 IDE (in) setup time t20 IDE (in) holdtime t21 IDE (out) valid delay ( t22 IDE (out) valid delay ( t18 t14 t19 t20 t16 t21 t22 Min (ns) Typ (ns) 0.3 T0-1.4 T0/2-1.05 0.35 T0/2+0.9 1.6 1.1 5.45 -4.40 T0+3.80 -0.1 ST18-AU1 Max (ns) 0 73/87 ...
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... ST18-AU1 18.3.3 E-bus (X direct extension) CLKOUT INCYCLE t29 EA t24 XBSE t23 t25 XRDE_EXRD ED (in) XWRE_EXWR ED (out) No PARAMETER t23 XBSE low delay t24 XBSE high delay t25 XRDE_EXRD low delay t26 XRDE_EXRD high delay t27 XWRE_EXWR low delay t28 XWRE_EXWR high delay t29 ...
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... EIWR high delay t39 EA valid delay t40 EA hold time t41 ED (in) setup time t42 ED (in) hold time t43 ED (out) valid delay ( t44 ED (out) valid delay ( t39 t36 t35 t41 t37 t38 t43 Min (ns) Typ (ns) ST18-AU1 t40 t42 t44 Max (ns) 2.55 1.4 2.15 1.7 T0+4.15 T0+3.90 8.25 -6.55 2 1.95 75/87 ...
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... ST18-AU1 18.3.5 E-bus (X BSU) CLKOUT INCYCLE EA XRDE_EXRD ED (in) XWRE_EXWR ED (out) No PARAMETER t45 XRDE_EXRD low delay t46 XRDE_EXRD high delay t47 XWRE_EXWR low delay t48 XWRE_EXWR high delay t49 EA valid delay t50 EA hold time t51 ED (in) setup time t52 ED (in) hold time t53 ...
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... EA valid delay t60 EA hold time t61 ED (in) setup time t62 ED (in) hold time t63 ED (out) valid delay ( t64 ED (out) valid delay ( t59 t56 t55 t61 t57 t58 t63 Min (ns) Typ (ns) T0+4.1 T0+4.05 -7.55 ST18-AU1 t60 t62 t64 Max (ns) 2.85 1.4 2.85 1.4 9.2 4.20 2.05 77/87 ...
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... ST18-AU1 18.3.7 D950 control CLK0 t4 CLKOUT t3 INCYCLE RESET IRQ LP P(in) P(out) No PARAMETER t65 RESET setup time t66 RESET hold time t67 IRQ setup time t68 IRQ min. pulse duration,low t69 LP setup time t70 LP min. pulse duration,low t71 P (in) setup time t72 P (in) hold time ...
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... HDA (out delay max t80 START Condition setup t81 STOP Condition setup * = External R load to Vdd = ** Rise time defined by External Rload t77 t76 t78 t79 t81 Min (ns) Typ (ns) 2xT0 + 1.1ns 2xT0 + 6.45ns 4xT0 + 6.45ns ST18-AU1 Max (ns) 0 TBD TBD TBD TBD 79/87 ...
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... ST18-AU1 18.3.9 PCM and SPDIF CLK1 t9 SCLK t82 SCLKPCM t84 WSPCM t86 PCMOUT0/1/2 t88 SPDIFOUT No PARAMETER t82* SCLKPCM high delay t83* SCLKPCM low delay t84 WSPCM high delay t85 WSPCM low delay t86 PCMOUT0/1/2 high delay t87 PCMOUT0/1/2 low delay t88 SPDIFOUT high delay ...
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... CLK1 rise to DREQ0 propagation time * For this time, CLKDIN0 is halted by DREQ0. t90t91 t90 t91 t92 t93 t92 t93 t94 SLAVE MODE t97 t97 t99 t98 t100 t102 MASTER MODE Min (ns) ST18-AU1 t90 t91 t92 t93 t95 t96 t99 t101 t102 Typ (ns) Max (ns) -1.45 2.10 -2.95 3.45 7.05 12.90 9 ...
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... ST18-AU1 18.3.11 I2S Data Input 1 CLKDIN1 t103 t104 WSDIN1 t105 t106 DIN1 CLK1 t107 CLKDIN1 t109 WSDIN1 t111 DIN1 No PARAMETER t103 WSDIN1 to CLKDIN1 setup time t104 CLKDIN1 to WSDIN1 hold time t105 DIN1 to CLKDIN1 setup time t106 CLKDIN1 to DIN1 hold time t107 CLK1 rise to CLKDIN1 fall propagation time ...
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... ST18-AU1 PACKAGE SPECIFICATIONS 19.1 ST18-AU1 package pinout The ST18-AU1 is available in a 160 pin plastic quad flat pack (PQFP) package. Table 19.1 ST18-AU1 package pinout Pin name Pin no. Pin name 1 GNDE VDD 2 VDDE GND 3 IDE<15> VDDE 4 IDE<14> GNDE 5 IDE<13> PCM_OUT0 6 IDE<12> PCM_OUT1 7 IDE<11> PCM_OUT2 8 IDE< ...
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... ST18-AU1 Pin name Pin no. Pin name 33 IAE<5> XRDE_EXRD 34 IAE<4> XWRE_EXWR 35 IAE<3> EYWR 36 IAE<2> EIWR 37 IAE<1> EIRD 38 IAE<0> EYRD 39 GNDE VDD 40 VDDE GND 19.2 160 pin PQFP package dimensions Table 19.2 160 pin PQFP package dimensions REF ...
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... Figure 19.1 Package diagram ST18-AU1 85/87 ...
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... ST18-AU1 20 DEVICE ID The identification code for the ST18-AU1 52BD041, where manufacturing revision number reserved by SGS-THOMSON. bit 31 Mask rev ST18 family reserved Defined IEEE 1149.1 standard. ...
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Information furnished is believed to be accurate and reliable. However, SGS-TH OMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from ...