ST16C654 EXAR [Exar Corporation], ST16C654 Datasheet - Page 24

• Manufacturer Part Number: ST16C654
• Description: 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
• Manufacturer: EXAR [Exar Corporation]

   
See “Receiver” on page15.
See “Transmitter” on page13.
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
When the receive FIFO (FCR BIT-0 = 1) and receive interrupts (IER BIT-0 = 1) are enabled, the RHR interrupts
(see ISR bits 2 and 3) status will reflect the following:
A.
B.
C.
4.0 INTERNAL REGISTER DESCRIPTIONS
4.1
4.2
4.3
4.3.1
A
A2-A0
X X X
DDRESS
0 1 0
1 0 0
1 0 1
1 1 0
1 1 1
T
Receive Holding Register (RHR) - Read- Only
Transmit Holding Register (THR) - Write-Only
Interrupt Enable Register (IER) - Read/Write
ABLE
IER versus Receive FIFO Interrupt Mode Operation
XOFF1 RD/WR
XOFF2 RD/WR
FSTAT
XON1 RD/WR
XON2 RD/WR
N
R
EFR
AME
10: INTERNAL REGISTERS DESCRIPTION.
EG
RD/WR
R
W
RD
EAD
RITE
/
RDYD#
Enable
CTS#
B
Auto
Bit-7
Bit-7
Bit-7
Bit-7
RX-
IT
-7
RDYC#
Enable
RTS#
B
Auto
Bit-6
Bit-6
Bit-6
Bit-6
RX-
IT
-6
Enhanced Registers
Special
RDYB#
Select
B
Char
Bit-5
Bit-5
Bit-5
Bit-5
RX-
IT
-5
24
IER [7:4],
ISR [5:4],
FCR[5:4],
MCR[7:5]
RDYA#
Enable
B
Bit-4
Bit-4
Bit-4
Bit-4
RX-
IT
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
-4
S
HADED BITS ARE ENABLED WHEN
RDYD#
B
ware
Soft-
Flow
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Cntl
TX-
IT
-3
RDYC#
B
Soft-
ware
Flow
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Cntl
TX-
IT
-2
RDYB#
B
Soft-
ware
Flow
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Cntl
TX-
IT
-1
RDYA#
EFR B
B
Soft-
ware
Flow
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Cntl
TX-
ST16C654/654D
IT
-0
IT
address lines
FSRS# pin is
a logic 0. No
-4=1
LCR=0
C
required.
REV. 5.0.0
OMMENT
X
BF