ST24FC21 STMICROELECTRONICS [STMicroelectronics], ST24FC21 Datasheet - Page 10

• Manufacturer Part Number: ST24FC21
• Description: 1 Kbit x8 Dual Mode Serial EEPROM for VESA PLUG & PLAY
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST24LC21B, ST24LW21, ST24FC21, ST24FC21B, ST24FW21
Table 7. AC Characteristics, I
(T
Notes: 1. Sampled only, not 100% tested.
I
The ST24xy21 supports the I
tocol defines any device that sends data onto the
bus as a transmitter and any device that reads the
data as a receiver. The device that controls the data
transfer is known as the master and the other as
the slave. The master will always initiate a data
transfer and will provide the serial clock for syn-
chronisation. The ST24xy21 are always slave de-
vices in all communications.
Start Condition. START is identified by a high to
low transition of the SDA line while the clock SCL
is stable in the high state. A START condition must
precede any command for data transfer. Except
during a programming cycle, the ST24xy21 con-
tinuously monitor the SDA and SCL signals for a
START condition and will not respond unless one
is given.
The ST24LC21B, ST24LW21, ST24FC21 and
ST24FW21 are not executing a START condition if
this START condition happens at any time inside a
byte. The ST24FC21B executes a START condi-
tion when this START condition happens at any
time inside a byte.
10/22
2
C Bus Background
t
t
t
A
t
CH1CH2
DH1DH2
Symbol
CL1CL2
DL1DL2
t
CHDX
= –40 to 85 C; V
t
t
t
t
t
t
t
t
t
CHDH
CHCL
CLCH
DXCX
DHDL
CLQV
CLQX
DLCL
CLDX
t
f
W
2. For a reSTART condition, or following a write cycle.
C
(2)
(1)
(1)
(1)
(1)
t
t
t
t
t
SU:STO
SU:STA
HD:STA
HD:DAT
SU:DAT
t
t
t
f
HIGH
t
Alt
LOW
t
BUF
t
SCL
WR
t
t
t
t
DH
AA
R
R
F
F
CC
= 3.6 to 5.5V or V
Clock Rise Time
Clock Fall Time
SDA Rise Time
SDA Fall Time
Clock High to Input Transition
Clock Pulse Width High
Input Low to Clock Low (START)
Clock Low to Input Transition
Clock Pulse Width Low
Input Transition to Clock Transition
Clock High to Input High (STOP)
Input High to Input Low (Bus Free)
Clock Low to Data Out Valid
Clock Low to Data Out Transition
Clock Frequency
Write Time
2
C protocol. This pro-
2
C Bidirectional Mode for Clock Frequency = 400kHz
Parameter
CC
= 2.5 to 5.5V)
Stop Condition. STOP is identified by a low to high
transition of the SDA line while the clock SCL is
stable in the high state. A STOP condition termi-
nates communication between the ST24xy21 and
the bus master. A STOP condition at the end of a
Read command (after the No ACK) forces the
standby state. A STOP condition at the end of a
Write command triggers the internal EEPROM
write cycle.
The ST24LC21B, ST24LW21, ST24FC21 and
ST24FW21 are not executing a STOP condition if
this STOP condition happens at any time inside a
byte. The ST24FC21B executes a STOP condition
when this STOP condition happens at any time
inside a byte.
Acknowledge Bit (ACK). An acknowledge signal
is used to indicate a successfull data transfer. The
bus transmitter, either master or slave, will release
the SDA bus after sending 8 bits of data. During the
9th clock pulse period the receiver pulls the SDA
bus low to acknowledge the receipt of the 8 bits of
data.
Data Input. During data input, the ST24xy21 sam-
ple the SDA bus signal on the rising edge of the
clock SCL. Note that for correct device operation
Min
600
600
600
100
600
200
200
1.3
1.3
20
20
0
Max
300
300
300
300
900
400
10
Unit
kHz
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
s