ade3000 STMicroelectronics, ade3000 Datasheet - Page 53
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ade3000
Manufacturer Part Number
ade3000
Description
Lcd Display Engines With Integrated Dvi, Adc And Yuv Ports
Manufacturer
STMicroelectronics
Datasheet
1.ADE3000.pdf
(88 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ade3000SX
Manufacturer:
ST
Quantity:
20 000
ADE3XXX
OSQ_CONTROL
OSQ_CLOCK_FRAC
OSQ_OUT_HTOTAL_L
OSQ_OUT_HTOTAL_H
OSQ_OUT_VTOTAL_MIN_L
OSQ_OUT_VTOTAL_MIN_H
OSQ_VTOTAL_MAX_L
OSQ_VTOTAL_MAX_H
OSQ_VERTEN_DLY_E_L
OSQ_VERTEN_DLY_E_M
OSQ_VERTEN_DLY_E_H
OSQ_VERTEN_DLY_O_L
OSQ_VERTEN_DLY_O_M
Register Name
Table 19: Output Sequencer Registers (Sheet 1 of 2)
0x0BC1
0x0BC2
0x0BC3
0x0BC4
0x0BC5
0x0BC6
0x0BC7
0x0BC8
0x0BC9
0x0BCA
0x0BCB
0x0BCC
0x0BCD
Addr
R
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Mode
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
[7:0]
[7:0]
[7:4]
[3:0]
[7:0]
[7:4]
[3:0]
[7:0]
[7:4]
[3:0]
[7:0]
[7:0]
[7:4]
[3:0]
[7:0]
[7:0]
Bits
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Default
out_vmax detected, sticky bit
out_vmax detect reset
interlace enable
fractional line extend
0: +1
1: +2
frame lock reference
0: last input pixel
1: first input pixel
frame lock selection
0: last line variable
1: fixed line length
shutdown ready - current frame has completed,
panel can now be shut down
run sequencer when 1, otherwise stop at the
end of the frame and set shutdown ready flag
(bit [1])
the fraction of lines (/256) that are extended
nominal output horizontal total [7:0]
Reserved
nominal output horizontal total [11:8]
minimum output vertical total, used to rearm for
vert_enab trigger [7:0]
Reserved
minimum output vertical total, used to rearm for
vert_enab triggers [11:8]
maximum output vertical total, prevents panel
burn with loss of vert_enab trigger [7:0]
Reserved
maximum output vertical total, prevents panel
burn with loss of vert_enab triggers [11:8]
delay of the vert_enab signal to the reset of the
horizontal and vertical counters, even and non-
interlaced modes [15:0]
Reserved
delay of the vert_enab signal to the reset of the
horizontal and vertical counters, even and non-
interlaced [19:16]
delay of the vert_enab signal to the reset of the
horizontal and vertical counters, odd frame in
interlace mode only [15:0]
Output Sequencer Block
Description
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