SM59264IHHK SYNCMOS [SyncMOS Technologies,Inc], SM59264IHHK Datasheet

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... The on-chip flash memory can be programmed in either paral- lel or serial interface with its ISP feature. Ordering Information yywwv SM59264ihhk yy: year, ww:week v: version identifier { , A, B, ...} i: process identifier hh: working clock in MHz {25, 40} k: package type postfix {as below table} ...

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SyncMOS Technologies Inc. May 2002 Pin Configurations SPWM3/P1 SM59264 P1.7 RES 10 ihhJ RXD/P3.0 11 P4.3 12 44L PLCC TXD/P3.1 13 #INT0/P3.2 (Top View) 14 ...

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SyncMOS Technologies Inc. May 2002 Block Diagram Timer 2 Timer 1 WDT RES Reset Circuit Vdd Power Vss Circuit Interrupt Circuit XTAL2 XTAL1 Timing #EA Generator ALE #PSEN Instruction Register Port 0 Latch SPWM Port 0 Driver & Mux Specifications ...

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SyncMOS Technologies Inc. May 2002 Pin Descriptions 40L 44L 44L PDIP QFP PLCC Symbol Pin# Pin# Pin T2/P1 T2EX/P1 SPWM0/P1 SPWM1/P1 SPWM2/P1 ...

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SyncMOS Technologies Inc. May 2002 Special Function Register (SFR) The address $80 to $FF can be accessed by direct addressing mode only. Address $80 to $FF is SFR area. The following table lists the SFRs which are identical to general ...

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SyncMOS Technologies Inc. May 2002 Addr SFR Reset F4H ISPFAH 00H F5H ISPFAL 00H F6H ISPFD 00H F7H ISPC 0*0***00 Extension Function Description 1. Memory Structure The SM59264 is the general 8052 hardware core to integrate the expanded 768 byte ...

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SyncMOS Technologies Inc. May 2002 Note: The single flash block address structure for doing the ISP function to the on-chip data flash as well as program ROM flash. 1.2 Data Memory The SM59264 has 1K bytes on-chip RAM, 256 bytes ...

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SyncMOS Technologies Inc. May 2002 FF Higher 128 bytes SFR 80 7F Lower 128 bytes 00 Note: External RAM address structure for reading the on-chip data flash. 1.2.1 Data Memory - Lower 128 byte ($00 to $7F, Bank 0 & ...

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SyncMOS Technologies Inc. May 2002 BS3 BS2 With ...

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SyncMOS Technologies Inc. May 2002 1.4 Data Flash - ($0000 to $FFFF) SM59264 has 64K byte on-chip data flash embedded. The 64KB on-chip data flash can be read by direct external addressing mode (by MOVX instruction) which means user does ...

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SyncMOS Technologies Inc. May 2002 One page of data RAM is 256 bytes. The port 0, port2, port3.6 and port3.7 can be used as general purpose I/O pin while port0 is open-drain structure. System Control Register (SCONF, $BF) bit-7 Read: ...

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SyncMOS Technologies Inc. May 2002 2. Port 4 for PLCC or QFP package: The bit addressable port 4 is available with PLCC or QFP package. The port 4 has only 4 pins and its port address is located at 0D8H. ...

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SyncMOS Technologies Inc. May 2002 After N determined, SM59264 will reserve the ISP service program space downward from the top of the program address $FFFF. The start address of the ISP service program located at $Fx00 while ...

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SyncMOS Technologies Inc. May 2002 User can initiate general 8052 UART function to initiate the ISP service program. After ISP service program executed, user need to reset the SM59264, either by hardware reset or by WDT, or jump to the ...

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SyncMOS Technologies Inc. May 2002 ISP Registers - Flash Data Register (ISPFD, $F6) bit-7 Read: FD7 Write : Reset value : 0 FD7 ~FD0 : flash data for ISP function The ISPFD provide the 8-bit data for ISP function ISP ...

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SyncMOS Technologies Inc. May 2002 To perform byte program/page erase ISP function, user need to specify flash address at first. When performing page erase function, SM59264 will erase entire page which flash address indicated by ISPFAH & ISPFAL registers located ...

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SyncMOS Technologies Inc. May 2002 4.1 Watch Dog Timer Registers: Watch Dog Timer Registers - WDT Control Register (WDTC, $9F) bit-7 Read : WDTE Write: Reset value: 0 WDTE: Watch Dog Timer enable bit CLEAR: Watch Dog Timer reset bit ...

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SyncMOS Technologies Inc. May 2002 Watch Dog Timer Register - System Control Register (SCONF, $BF) bit-7 Read : WDR Write : Reset value : 0 The bit 7 (WDR) of SCONF is Watch Dog TImer Reset bit. It will be ...

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SyncMOS Technologies Inc. May 2002 bit-7 Read: Unused Write: Reset value: * SPFS[1:0]: These two bits is 2’s power parameter to form a frequency divider for input clock. SPFS1 SPFS0 SPWM Registers ...

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SyncMOS Technologies Inc. May 2002 1st cycle frame 2nd cycle frame 3rd cycle frame 32T 32T 16T 16T 1T (narrow pulse inserted by BRM0[2:0] setting, here BRM0[2:0]=3) SPWM clock = Fosc / 2^(SPFS[1:0]+1) The SPWM output ...

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SyncMOS Technologies Inc. May 2002 Operating Conditions Symbol Description TA Operating temperature TS Storage temperature VCC5 Supply voltage Fosc 16 Oscillator Frequency Fosc 25 Oscillator Frequency Fosc 40 Oscillator Frequency DC Characteristics (12MHz, typical operating conditions, valid for SM59264 series) ...

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SyncMOS Technologies Inc. May 2002 AC Characteristics (16/25/40 MHZ, operating conditions; CL for Port 0, ALE and PSEN Outputs=150PF; CL for all Other Output=80pF) Symbol Parameter T LHLL ALE pulse width T AVLL Address Valid to ALE low T LLAX ...

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SyncMOS Technologies Inc. May 2002 ISP Test Conditions (40 MHZ, typical operating conditions, valid for SM59264 series) Symbol Chip erase Page erase Program Protect Application Reference Valid for SM59264 X'tal 3MHz 6MHz ...

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SyncMOS Technologies Inc. May 2002 Data Memory Read Cycle Timing T12 T1 T2 OSC 1 ALE #PSEN #RD PORT2 PORT0 INST in Float Program Memory Read Cycle Timing T2 T12 T1 OSC ALE 1 #PSEN #RD,#WR PORT2 PORT0 Float Specifications ...

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SyncMOS Technologies Inc. May 2002 Data Memory Write Cycle Timing T1 T2 T12 OSC 1 ALE #PSEN #WR PORT2 PORT0 INST Float I/O Ports Timing T6 X1 inputs P0,P1 inputs P2,P3 Output by Mov Px,Src RxD at Serial Port Shift ...

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SyncMOS Technologies Inc. May 2002 Timing Critical, Requirement of External Clock (Vss=0.0V is assumed) Vdd-0.5V 0.45V Tm.I External Program Memory Read Cycle #PSEN TLHLL ALE TAVLL PORT 0 PORT 2 Tm.II External Data Memory Read Cycle #PSEN ALE #RD TAVLL ...

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SyncMOS Technologies Inc. May 2002 Tm.III External Data Memory Write Cycle #PSEN TLHLL ALE TAVLL #WR PORT 0 from Ri or DPL PORT 2 Specifications subject to change without notice,contact your sales representatives for the most recent information. TLLYL TWLWH ...

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SyncMOS Technologies Inc. May 2002 40L 600mil PDIP Information Note: 1.Dimension D Max & include mold flash or tie bar burrs. 2.Dimension E1 does not include inter lead flash. 3.Dimension D & E1 include mold mismatch ...

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SyncMOS Technologies Inc. May 2002 44L Plastic Chip Carrier (PLCC Note: 1.Dimension D & E does not include inter lead flash. 2.Dimension b1 does not include dam bar protrusion/ intrusion. 3.Controlling dimension: Inch 4.General appearance ...

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SyncMOS Technologies Inc. May 2002 44L Plastic Quad Flat Package Note: Dimension D1 and E1 do not include mold protrusion. Allowance protrusion is 0.25mm per side. Dimension D1 and E1 do include mold mismatch and are determined ...

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SyncMOS Technologies Inc. May 2002 Company Advantech 7F, No.98, Ming-Chung Rd., Shin-Tien City, Taipei, Taiwan, ROC Web site: http://www.aec.com.tw Caprilion P.O. Box 461 KaoHsiung, Taiwan, ROC Web site: http://www.market.net.tw/ ~ cap/ Hi-Lo 4F, No. 20, 22, LN, 76, Rui Guang ...

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SyncMOS Technologies Inc. May 2002 Feedback / Inquiry To : SyncMOS Technologies, Inc. Attn : MKT / Customer Service Dept. Fax : 886-3-5792960 : 886-3-5780493 Tel : 886-3-5792988 : 886-3-5792926 Request customer logo as below: Description: Specifications subject to change ...