gc41c501g0-sp8i CORERIVER Semiconductor, gc41c501g0-sp8i Datasheet - Page 18
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gc41c501g0-sp8i
Manufacturer Part Number
gc41c501g0-sp8i
Description
4-bit Microcontrollers With Reduced 8051 Architecture With Reduced 8051 Architecture
Manufacturer
CORERIVER Semiconductor
Datasheet
1.GC41C501G0-SP8I.pdf
(64 pages)
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Preliminary
6.4. CPU Timing
CPU takes 6 clocks for a machine cycle.
Any instruction except branch instructions completes in one machine cycle.
All branch instruction consumes 2 machine cycles whether the branch is taken or not.
The state of SFR, I/O ports, or IFF flags changes at the end of an instruction (S6).
System Clock
CPU State
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
Program Counter
N
N+1
Instruction
Op. Code (N-1)
Op. Code (N)
Register
Machine Cycle
Machine Cycle
Fetch Cycle N
Fetch Cycle N+1
Execution Cycle N-1
Execution Cycle N
[18]
ATOM1.0 Family
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