k9f2808q0c-dcb0 Samsung Semiconductor, Inc., k9f2808q0c-dcb0 Datasheet - Page 18

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k9f2808q0c-dcb0

Manufacturer Part Number
k9f2808q0c-dcb0
Description
16m X 8 Bit , 8m X 16 Bit Nand Flash Memory
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
K9F2808Q0C-DCB0,DIB0
K9F2808U0C-YCB0,YIB0
K9F2808U0C-DCB0,DIB0
System Interface Using CE don’t-care.
For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal
528byte/264word page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addi-
tion, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading
and reading would provide significant savings in power consumption.
Figure 6. Program Operation with CE don’t-care.
CLE
CE
WE
ALE
Figure 7. Read Operation with CE don’t-care.
CE
WE
I/Ox
R/B
CLE
ALE
WE
CE
RE
I/Ox
t
CS
00h
80h
Start Add.(3Cycle)
Start Add.(3Cycle)
t
K9F2816Q0C-DCB0,DIB0
K9F2816U0C-YCB0,YIB0
K9F2816U0C-DCB0,DIB0
WP
On K9F2808U0C_Y,P or K9F2808U0C_V,F
CE must be held
low during tR
t
CH
t
R
Data Input
18
K9F2808U0C-VCB0,VIB0
I/O
CE
RE
0
~
15
CE don’t-care
CE don’t-care
t
Data Output(sequential)
CEA
t
REA
FLASH MEMORY
Data Input
out
10h

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