w89c926 Winbond Electronics Corp America, w89c926 Datasheet - Page 5

• Manufacturer Part Number: w89c926
• Description: Pcmcia Ethernet Network Twisted Pair Interface Controller
• Manufacturer: Winbond Electronics Corp America

Pin Description, continued
Memory Support Interface
MSA0-7
MSA8-10
MSA11-13
MSA14-16
MSD0-2
MSD3-7
EECS/
RCS
MSRD
FCS
NAME
90-97
82, 81, 78
80, 98, 84
99, 69, 70
NUMBER
89-87
71-75
77
76
79
I/O/3SH
IO/3SH
O/3SH
O/TTL
O/TTL
O/TTL
TYPE
I/3SH
Memory Support Address:
Latched address used to decode accesses to the on-
board memory.
Memory Support Data Bus:
Bidirectional on-board memory data bus.
EEPROM Interface:
During the EEPROM auto-load or read/write sequence,
MSD0 is used as a serial data input/output from/to
EEPROM, MSD1 outputs EEPROM commands to
EEPROM, and MSD2 sends a clock with a period of 1.2
microseconds. This function is available only when
EECS/ FCS is low during H/W reset.
SRAM Chip Select:
enable during buffer memory access.
Nonvolatile Memory Chip Select:
EECS/ FCS is asserted by the PENTIC+ for chip enable
during nonvolatile memory access. It is active low for
flash memory enable and active high for EEPROM chip
enable.
Nonvolatile Memory Detection:
During H/W reset, the PENTIC+ will determine the
existing nonvolatile memory type by sampling the
voltage level on this pin. If this pin is externally pulled
high with a 470K ohm resistor, the PENTIC+ will
determine that the memory is a flash memory; if the pin
is pulled low with a 470K ohm resistor, it will determine
that the memory is an EEPROM.
Memory Support Read:
from the on-board memory. Both SRAM and flash
memory use MSRD as the read command strobe.
RCS is asserted by the PENTIC+ for SRAM chip
MSRD is asserted by the PENTIC+ to strobe read data
- 5 -
Publication Release Date: January 1996
DESCRIPTION
W89C926 PENTIC+
Revision A1