w89c926 Winbond Electronics Corp America, w89c926 Datasheet - Page 40

• Manufacturer Part Number: w89c926
• Description: Pcmcia Ethernet Network Twisted Pair Interface Controller
• Manufacturer: Winbond Electronics Corp America

PCMCIA bus slave access, continued
Notes: 1. This is the timing for insert wait states. WAIT is asserted if the core cannot service the access immediately; it will hold
asserted until the core is ready, causing the system to insert wait states.
SYMBOL
T16b
T23a
T23b
T26a
T26b
T27a
T27b
T17
T18
T19
T20
T21
T22
T24
T25
T28
2. This is the timing for shared memory access.
3. This is the timing for I/O access.
4. IOIS16 is asserted for 16-bit I/O transfers.
5. Read data valid is referenced to WAIT when wait states are inserted.
6. If no wait states are inserted, read data valid can be referenced from OE, IORD.
7. REG is asserted for I/O access and it is deasserted for common memory access.
8. INPACK is asserted only for I/O read operation.
9. This is a shared memory access without bus contention.
10. This is the timing for SRAM-15.
HA0-16 deasserted to IOIS16 deasserted.
MSA0-14 asserted t0 WAITdeasserted.
MSD odd byte read data valid to HD0-15 read data
valid.
MSD odd byte read data hold after MSRD
deasserted.
MSD odd byte read data hold after MSRD
deasserted.
MSA0-14 valid to MSWR asserted.
second MSWR asserted before WAIT deasserted.
MSD write data setup before MSWR deasserted.
MSD write data setup before MSWR deasserted.
MSD write data hold after MSWR deasserted.
MSD write data hold after MSWR deasserted.
Command deasserted to next command asserted
IORD, IOWR deasserted to HA0-16 deasserted.
IORD deasserted to INPACK deasserted.
CE1 ,2 asserted to RCS asserted.
OE, asserted to ROE asserted.
DESCRIPTION
- 40 -
Note.10
Note.10
Note 4
Note 1
Note 2
Note 1
Note.10
W89C926 PENTIC+
MIN.
150
20
35
10
5
3
0
5
3
-
-
-
-
-
-
-
MAX.
265
265
215
140
30
40
35
-
-
-
-
-
-
-
-
-
UNIT
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS