em78p5830aa ELAN Microelectronics Corp, em78p5830aa Datasheet - Page 17

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em78p5830aa

Manufacturer Part Number
em78p5830aa
Description
8-bit Micro-controller 8-bit Micro-controller
Manufacturer
ELAN Microelectronics Corp
Datasheet
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
PAGE2 : (undefined) not allowed to use
PAGE3 (DT2L: the Least Significant Byte ( Bit 7 ~ Bit 0 ) of Duty Cycle of PWM2)
RA (PLL, Main clock selection, Watchdog timer)
PAGE0 (PLL enable bit, Main clock selection bits, Watchdog timer enable bit)
PWM2[7] PWM2[6] PWM2[5] PWM2[4] PWM2[3] PWM2[2] PWM2[1] PWM2[0]
R/W-0
R/W-0
Bit 0(WDTEN) : Watch dog control bit
Bit 3 ~ Bit 5 (CLK0 ~ CLK2) : MAIN clock selection bits
Bit 6(PLLEN) : PLL's power control bit which is CPU mode control register
The address for data RAM is accessed from R8 PAGE1. The data RAM bank is selected by R7 PAGE1 Bit0
(RAM_B0).
7
A specified value keeps the output of PWM2 to stay at high until the value matches with TMR2.
7
0
User can use WDTC instruction to clear watch dog counter. The counter 's clock source is 32768/2 Hz. If
the prescaler assigns to TCC. Watch dog will time out by (1/32768 )*2 * 256 = 15.616mS. If the
prescaler assigns to WDT, the time of time out will be more times depending on the ratio of prescaler.
0/1
Bit 1~Bit 2 : Unused, these 2 bits are not allowed to use.
User can choose different frequency of main clock by CLK1 and CLK2. All the clock selection is list below.
0/1
If enable PLL, CPU will operate at normal mode (high frequency). Otherwise, it will run at green mode
(low frequency, 32768 Hz).
PLLEN
1
1
1
1
1
1
1
1
0
disable/enable
disable PLL/enable PLL
R/W-0
PLLEN
R/W-0
6
6
don’t care don’t care don’t care 32.768kHz
CLK2
0
0
0
0
1
1
1
1
32.768kHz
Sub-clock
R/W-0
PLL circuit
CLK2
R/W
5
5
CLK1
Fig.7 The relation between 32.768kHz and PLL
0
0
1
1
0
0
1
1
R/W-0
CLK1
R/W
4
4
CLK0
0
1
0
1
0
1
0
1
447.8293kHz ~14.3MHz
CLK2 ~ CLK0
R/W-0
CLK0
R/W
3
3
ENPLL
Sub clock
32.768kHz
32.768kHz
32.768kHz
32.768kHz
32.768kHz
32.768kHz
32.768kHz
Can’t allowed to use
15
R/W-0
2
X
-
2
1
0
switch
MAIN clock
447.829kHz
895.658kHz
1.791MHz
3.582MHz
7.165MHz
10.747MHz
14.331MHz
don’t care
R/W-0
1
-
X
1
System
clock
R/W-0
CPU clock
447.829kHz (Normal mode)
895.658kHz (Normal mode)
1.791MHz (Normal mode)
3.582MHz (Normal mode)
7.165MHz (Normal mode)
10.747MHz (Normal mode)
14.331MHz (Normal mode)
32.768kHz (Green mode)
WDTEN
0
R/W-0
8-bit Micro-controller
0
12/1/2004 V1.6
EM785830AA

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