em78p5830aa ELAN Microelectronics Corp, em78p5830aa Datasheet - Page 12

• Manufacturer Part Number: em78p5830aa
• Description: 8-bit Micro-controller 8-bit Micro-controller
• Manufacturer: ELAN Microelectronics Corp

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* This specification is subject to be changed without notice.
Bit 3 (SCES) : SPI clock edge selection bit
Bit 4 (SE) : SPI shift enable bit
Bit 5 (SRO) : SPI read overflow bit
Bit 6 (SPIE) : SPI enable bit
Bit 7 (RBF) : SPI read buffer full flag
R5 page1
If PLL is disabled, the instruction clock is 32.768kHz/2
1
0
1
0
<Note> This bit has to be reset in software.
1
0
1
0
1
0
Fig. 4 shows how SPI to communicate with other device by SPI module. If SPI is a master controller, it
sends clock through the SCK pin. An 8-bit data is transmitted and received at the same time. If SPI,
however, is defined as a slave, its SCK pin could be programmed as an input pin. Data will continue to be
shifted on a basis of both the clock rate and the selected edge.
Fsco=0.895MHz/2
Data shifts out on falling edge, and shifts in on rising edge. Data is hold during the high level.
Data shifts out on rising edge, and shifts in on falling edge. Data is hold during the low level.
Start to shift, and keep on 1 while the current byte is still being transmitted.
Reset as soon as the shifting is complete, and the next byte is ready to shift.
A new data is received while the previous data is still being hold in the SPIB register. In this situation,
No overflow, <Note> This can only occur in slave mode.
Enable SPI mode
Disable SPI mode
Receive is finished, SPIB is full.
Receive is not finish yet, SPIB is empty.
the data in SPIS register will be destroyed. To avoid setting this bit, users had better to read SPIB
register even if the transmission is implemented only.
SPIR register
Bit7
Master Device
SPIS Reg
Fig.4 Single SPI Master / Salve Communication
SPIW register
Bit 0
10
SDO
SDI
SCK
Fsco=32.768kHz/2.
SDO
SDI
SCK
Salve Device
SPI module
8-bit Micro-controller
12/1/2004 V1.6
EM785830AA