lc7073m Sanyo Semiconductor Corporation, lc7073m Datasheet
lc7073m
Related parts for lc7073m
lc7073m Summary of contents
Page 1
... The LC7073 and LC7073M operate from supply and are available in 18-pin DIPs and MFPs, respectively. Features • RDS error detection and correction. ...
Page 2
Block Diagram Pin Function ...
Page 3
Continued from preceding page ...
Page 4
Specifications Absolute Maximum Ratings +25˚ ...
Page 5
... Timing Diagrams The relationship between the LC7073 and LC7073M input data (RDS demodulated data output) and output data is shown in figure 1. Note The dotted lines show data start (DST) pulses when the data start control (DSTCTL) is LOW. The serial output data is delayed by one block between input and output. The error (ERR) and correction (COR) signals remain active if errors are detected continually ...
Page 6
CKPOL Input Read Delay CKPOL is read 1 ms after a reset as shown in figure 3. LC7073, 7073M Figure 2. Serial output data format and timing Figure 3. CKPOL input read delay No.3932–6/9 ...
Page 7
COREN and DSTCTL Input Read COREN and DSTCTL are monitored at intervals of one input clock cycle, and their logic states can be changed at any time. During sync detection, a change in input state occurs if either pin remains ...
Page 8
... Offset Words E and F The LC7070N/LC7070NM/LC7071NM recognizes offset words E and F and performs group sync detection. The LC7073/ LC7073M does not recognize offset words E and F–it only detects C’ and D. Input Data Bits If all data bits are 0, the LC7070N/LC7070NM/LC7071NM only recognizes offset word E. The LC7073/LC7073M does not recognize the offset word E block ...
Page 9
... If sync detection occurs during the first block (offset A), the LC7073/LC7073M starts data output with the second block (offset B). If sync detection occurs during the second or third block (offset B or C), and finishes before the end of the fourth block (offset D), the LC7073/LC7073M starts data output with the first block (offset A) of the second group. ...