lxt9763 Intel Corporation, lxt9763 Datasheet - Page 36

• Manufacturer Part Number: lxt9763
• Description: Fast Ethernet 10/100 Hex Transceiver With Full Mii
• Manufacturer: Intel Corporation

LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII
1.12.2.1
1.13
1.13.1
1.13.2
1.13.3
36
Event
LED
Note: The direct drive LED outputs in this diagram are shown as active Low.
Figure 16. LED Pulse Stretching
stretch
LED Pulse Stretching
The LED Configuration Register also provides optional LED pulse stretching to 30, 60, or 100 ms.
If during this pulse stretch period, the event occurs again, the pulse stretch time will be further
extended.
When an event such as receiving a packet occurs it will be edge detected and it will start the stretch
timer. The LED driver will remain asserted until the stretch timer expires. If another event occurs
before the stretch timer expires then the stretch timer will be reset and the stretch time will be
extended.
When a long event (such as duplex status) occurs it will be edge detected and it will start the stretch
timer. When the stretch timer expires the edge detector will be reset so that a long event will cause
another pulse to be generated from the edge detector which will reset the stretch timer and cause
the LED driver to remain asserted.
Boundary Scan (JTAG1149.1) Functions
LXT9763 includes a IEEE 1149.1 boundary scan test port for board level testing. All digital input,
output, and input/output pins are accessible.
Boundary Scan Interface
This interface consists of five pins (TMS,TDI,TDO,TCK and TRST). It includes a state machine,
data register array, and instruction register. The TMS and TDI pins are internally pulled up. TCK is
internally pulled down. TDO does not have an internal pull-up or pull-down.
State Machine
The TAP controller is a 16 Bit state machine driven by the TCK and TMS pins. Upon reset the
TEST_LOGIC_RESET state is entered. The state machine is also reset when TMS is High for five
TCK periods.
Instruction Register
After the state machine resets, the IDCODE instruction is always invoked. The decode logic
ensures the correct data flow to the Data registers according to the current instruction. Valid
instructions are listed in
stretch
Table
11.
Figure 16
shows how the stretch operation functions.
stretch
Datasheet