lxt9763 Intel Corporation, lxt9763 Datasheet - Page 11

• Manufacturer Part Number: lxt9763
• Description: Fast Ethernet 10/100 Hex Transceiver With Full Mii
• Manufacturer: Intel Corporation

Datasheet
1. Type Column Coding: I = Input, O = Output, OD = Open Drain
2. The LXT9763 supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an “X.Y” notation,
Pin#
196
197
198
199
195
191
194
79
82
83
84
60
61
62
63
42
43
44
45
24
25
26
27
77
59
41
23
75
57
39
21
76
58
40
22
71
70
69
66
where X is the register number (0-32) and Y is the bit number (0-15).
Table 1. LXT9763 MII Signal Descriptions
6
7
8
9
5
3
4
TXD0_0
TXD0_1
TXD0_2
TXD0_3
TXD1_0
TXD1_1
TXD1_2
TXD1_3
TXD2_0
TXD2_1
TXD2_2
TXD2_3
TXD3_0
TXD3_1
TXD3_2
TXD3_3
TXD4_0
TXD4_1
TXD4_2
TXD4_3
TXD5_0
TXD5_1
TXD5_2
TXD5_3
TX_EN0
TX_EN1
TX_EN2
TX_EN3
TX_EN4
TX_EN5
TX_ER0/TXD0_4
TX_ER1/TXD1_4
TX_ER2/TXD2_4
TX_ER3/TXD3_4
TX_ER4/TXD4_4
TX_ER5/TXD5_4
TX_CLK0
TX_CLK1
TX_CLK2
TX_CLK3
TX_CLK4
TX_CLK5
RXD0_0
RXD0_1
RXD0_2
RXD0_3
Symbol
Type
O
O
I
I
I
I
I
I
I
I
1
Transmit Data - Port 0. 4-bit parallel data to be transmitted from port 0 is clocked in
synchronously to TX_CLK. In symbol mode (16.11 = 1), the port transmit error
signal is re-mapped to provide a fifth data bit.
Transmit Data - Port 1. 4-bit parallel data to be transmitted from port 1 is clocked in
synchronously to TX_CLK. In symbol mode (16.11 = 1), the port transmit error
signal is re-mapped to provide a fifth data bit.
Transmit Data - Port 2. 4-bit parallel data to be transmitted from port 2 is clocked in
synchronously to TX_CLK. In symbol mode (16.11 = 1), the port transmit error
signal is re-mapped to provide a fifth data bit.
Transmit Data - Port 3. 4-bit parallel data to be transmitted from port 3 is clocked in
synchronously to TX_CLK. In symbol mode (16.11 = 1), the port transmit error
signal is re-mapped to provide a fifth data bit.
Transmit Data - Port 4. 4-bit parallel data to be transmitted from port 4 is clocked in
synchronously to TX_CLK. In symbol mode (16.11 = 1), the port transmit error
signal is re-mapped to provide a fifth data bit.
Transmit Data - Port 5. 4-bit parallel data to be transmitted from port 5 is clocked in
synchronously to TX_CLK. In symbol mode (16.11 = 1), the port transmit error
signal is re-mapped to provide a fifth data bit.
Transmit Enable - Ports 0 - 5. Active High input enables respective port transmitter.
This signal must be synchronous to the TX_CLK.
Transmit Coding Error - Ports 0 - 5. Valid during 100 Mbps operation only. This
signal must be driven synchronously to TX_CLK. When High, forces the respective
port to transmit Halt (H) code group.
Transmit Data - Ports 0 - 5. During symbol mode operation (16.11 = 1), these
signals are re-mapped to provide the fifth data bit (TXDn_4) for their respective ports
(n).
Transmit Clock - Ports 0 - 5. 25 MHz for 100 Mbps operation, 2.5 MHz for 10 Mbps
operation. The transmit data and control signals must always be synchronized to
TX_CLK by the MAC. The LXT9763 samples these signals on the rising edge of
TX_CLK.
Receive Data - Port 0. Data received at network port 0 is output in 4-bit parallel
nibbles, driven synchronously to RX_CLK. In symbol mode (16.11 = 1), the
receive error signals are re-mapped to provide a fifth data bit.
Fast Ethernet 10/100 Hex Transceiver with Full MII — LXT9763
Data Interface Pins
Signal Description
2
11