lxt9785 Intel Corporation, lxt9785 Datasheet - Page 161

• Manufacturer Part Number: lxt9785
• Description: Advanced 8-port 10/100 Mbps Phy Transceivers
• Manufacturer: Intel Corporation

4.14.2
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Note: High is defined by the IO voltage supply level selected (2.5V or 3.3V).
Link Hold-Off software control is enabled or disabled on individual ports by respectively setting or
clearing Register bit 0.11, the power-down bit, during normal operation. It is not required to have
previously enabled Link Hold-Off by hardware configuration.
Link Hold-Off is disabled if the external pin MDDIS is active. The MDDIS pin disables the MDIO
interface required to re-enable normal transmit and receive link operation. MDDIS is intended to
disable the MDIO management interface for unmanaged applications. Internal loopback circuitry
is unaffected in Link Hold-Off mode.
Operation
Link Hold-Off is implemented in one of the following two ways:
Link Hold-Off use by an external hardware pin is as follows:
Link Hold-Off is enabled on a per port basis by software control using the following two methods:
Method One:
This method requires that Link Hold-Off is enabled by the LINKHOLD pin during the last power-
up or hardware reset.
Method Two:
This method enables Link Hold-Off regardless of the LINKHOLD hardware configuration state.
1. Pull the LINKHOLD pin High with a pull-up resistor (approximately 5 k Ohms).
2. Power up the system or drive the reset pin active.
3. All ports are link disabled.
4. Program all ports to the desired configuration.
5. Clear Register Bit 0.11, power-down for each individual port.
6. Normal operation resumes on each port after Register bit 0.11 is cleared (see Table 83 for the
1. Set Register bit 0.15 to reset and re-enable Link Hold-Off for the desired port.
2. Program the PHY to the desired configuration.
3. Clear Register bit 0.11 (power-down) to disable Link Hold-Off.
4. Normal operation resumes.
1. Set Register bit 0.11(power-down) to enable Link Hold-Off for the desired port.
2. Program the PHY to the desired configuration.
3. Clear Register bit 0.11 (power-down) to disable Link Hold-Off.
4. Normal operation resumes.
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Using a hardware pin at power-up or hardware reset
Using software control through the MII Management (MDC/MDIO) interface.
recovery time).
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
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