lxt9785 Intel Corporation, lxt9785 Datasheet - Page 115

• Manufacturer Part Number: lxt9785
• Description: Advanced 8-port 10/100 Mbps Phy Transceivers
• Manufacturer: Intel Corporation

4.1.2
4.1.2.1
4.2
4.2.1
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Note: The BGA15 package does not support sectionalization.
The OSP-based LXT9785/LXT9785E provides improved data recovery, EMI performance and
power consumption.
Comprehensive Functionality
The LXT9785/LXT9785E performs all functions of the Physical Coding Sublayer (PCS) and
Physical Media Attachment (PMA) sublayer as defined in the IEEE 802.3 100BASE-X
specification. This device also performs all functions of the Physical Media Dependent (PMD)
sublayer for 100BASE-TX connections.
On power-up, the LXT9785/LXT9785E reads its configuration inputs to check for forced operation
settings. If not configured for forced operation, each port uses auto-negotiation/parallel detection to
automatically determine line operating conditions. If the PHY device on the other side of the link
supports auto-negotiation, the LXT9785/LXT9785E auto-negotiates with it using Fast Link Pulse
(FLP) Bursts. If the PHY partner does not support auto-negotiation, the LXT9785/LXT9785E
automatically detects the presence of either link pulses (10 Mbps PHY) or Idle symbols (100 Mbps
PHY) and set its operating conditions accordingly.
The LXT9785/LXT9785E provides half-duplex and full-duplex operation at 100 Mbps and 10
Mbps.
Sectionalization
The LXT9785/LXT9785E’s sectional design allows flexibility with large multiport MACs and
ASICs. With the use of the Section pin, the LXT9785/LXT9785E can be configured into a single 8-
port or two separate 4-port sections, each with its own MDIO (with separate MDC clock) and MII
data (with separate REFCLK/TxCLK/RxCLK clocks) interfaces. See
LXT9785/LXT9785E Typical SMII Quad Sectionalization Diagram” on page
“Intel® LXT9785/LXT9785E Typical SS-SMII Quad Sectionalization Diagram” on page 140,
Figure 26, “Intel® LXT9785/LXT9785E Typical RMII Quad Sectionalization Diagram” on
page
Interface Descriptions
10/100 Network Interface
The LXT9785/LXT9785E supports 10 Mbps and 100 Mbps (10BASE-T and 100BASE-TX)
Ethernet over twisted-pair, or 100 Mbps (100BASE-FX) Ethernet over fiber media. Each network
interface port consists of four external pins (two differential signal pairs). The pins are shared
between twisted-pair (TP) and fiber. The LXT9785/LXT9785E pinout is designed to interface
seamlessly with dual-high stacked RJ-45 connectors. Refer to
LXT9785E Network Interface Signal Descriptions – PQFP” on page 42
assignments.
The LXT9785/LXT9785E output drivers generate either 100BASE-TX, 10BASE-T, or 100BASE-
FX output. When not transmitting data, the device generates IEEE 802.3-compliant link pulses or
idle code. Input signals are decoded either as a 100BASE-TX, 100BASE-FX, or 10BASE-T input,
depending on the mode selected. Auto-negotiation/parallel detection or manual control is used to
determine the speed of this interface.
144.
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 11, “Intel® LXT9785/
Figure 16, “Intel®
for specific pin
134,
Figure 21,
and
117