lc7874e Sanyo Semiconductor Corporation, lc7874e Datasheet - Page 14

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lc7874e

Manufacturer Part Number
lc7874e
Description
Cd Graphics Decorder
Manufacturer
Sanyo Semiconductor Corporation
Datasheet
With the LC7860K/63 interface, SBCK is transmitted when SFSY is confirmed to be low approximately 2.2 µs after a
falling edge of SFSY is detected. With other interfaces, SBCK is transmitted when SFSY is confirmed to be high and
SBSY to be low approximately 2.2 µs after a rising edge of SFSY is detected.
(1) LC7860 interface [DSP pin names shown in parentheses]
(2) LC7861N/67 interface [DSP pin names shown in parentheses]
(3) LC78681/62X/63X Series interface
3. DRAM interface
4. CD graphic monitor pin: CDGM
Same as (2), except that the SBCK polarity is shifted inversely (shifted on rise of SBCK).
Interface pins: A0 to A7, DB0 to DB3, RAS, CAS, WE, OE
64K 4-bit DRAM is connected externally. The interface pins are set to high impedance by driving the CE1 pin
high. MPEG DRAM sharing is possible.
CDGM goes high once the LC7874E accepts any CD-G instruction. In the power-on state, once CDGM goes high it
remains high. It can be driven low by driving the INIT pin low or transferring an INIT command from the
microcontroller.
LC7874E
No. 5521-14/22

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